[llvm] 3673ba6 - [RISCV] Rename some variables to improve code clarity
Nitin John Raj via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 21 16:08:37 PDT 2023
Author: Nitin John Raj
Date: 2023-04-21T16:05:45-07:00
New Revision: 3673ba6992009d338ddbef71d75217394ede51cf
URL: https://github.com/llvm/llvm-project/commit/3673ba6992009d338ddbef71d75217394ede51cf
DIFF: https://github.com/llvm/llvm-project/commit/3673ba6992009d338ddbef71d75217394ede51cf.diff
LOG: [RISCV] Rename some variables to improve code clarity
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index da99723548f7f..1165672812eae 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -103,82 +103,82 @@ class VMVRSched<int n> : Sched<[
!cast<SchedReadWrite>("ReadVMov" #n #"V")
]>;
-class VLESched<string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVLDE_"#suffix),
+class VLESched<string lmul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVLDE_" #lmul),
ReadVLDX, ReadVMask
]>;
-class VSESched<string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVSTE_" # suffix),
- !cast<SchedReadWrite>("ReadVSTEV_" # suffix),
+class VSESched<string lmul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVSTE_" #lmul),
+ !cast<SchedReadWrite>("ReadVSTEV_" #lmul),
ReadVSTX, ReadVMask
]>;
-class VLSSched<int n, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVLDS" #n #"_" # suffix),
+class VLSSched<int eew, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVLDS" #eew #"_" #emul),
ReadVLDX, ReadVLDSX, ReadVMask
]>;
-class VSSSched<int n, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVSTS" #n #"_"#suffix),
- !cast<SchedReadWrite>("ReadVSTS" #n #"V_"#suffix),
+class VSSSched<int eew, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVSTS" #eew #"_" #emul),
+ !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul),
ReadVSTX, ReadVSTSX, ReadVMask
]>;
-class VLXSched<int n, string o,
- string dataSuffix = "WorstCase",
- string idxSuffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVLD" #o #"X" #n #"_" # dataSuffix),
+class VLXSched<int dataEEW, string isOrdered,
+ string dataEMUL = "WorstCase",
+ string idxEMUL = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVLD" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
ReadVLDX,
- !cast<SchedReadWrite>("ReadVLD" #o #"XV_" # idxSuffix), ReadVMask
+ !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #idxEMUL), ReadVMask
]>;
-class VSXSched<int n, string o,
- string dataSuffix = "WorstCase",
- string idxSuffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVST" #o #"X" #n #"_"#dataSuffix),
- !cast<SchedReadWrite>("ReadVST" #o #"X" #n #"_"#dataSuffix),
- ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV_"#idxSuffix), ReadVMask
+class VSXSched<int dataEEW, string isOrdered,
+ string dataEMUL = "WorstCase",
+ string idxEMUL = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
+ !cast<SchedReadWrite>("ReadVST" #isOrdered #"X" #dataEEW #"_" #dataEMUL),
+ ReadVSTX, !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #idxEMUL), ReadVMask
]>;
-class VLFSched<string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVLDFF_" # suffix),
+class VLFSched<string lmul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVLDFF_" #lmul),
ReadVLDX, ReadVMask
]>;
// Unit-Stride Segment Loads and Stores
-class VLSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew #"_"#suffix),
+class VLSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew #"_" #emul),
ReadVLDX, ReadVMask
]>;
-class VSSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew #"_"#suffix),
- !cast<SchedReadWrite>("ReadVSTEV_"#suffix),
+class VSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVSSEG" #nf #"e" #eew #"_" #emul),
+ !cast<SchedReadWrite>("ReadVSTEV_" #emul),
ReadVSTX, ReadVMask
]>;
-class VLSEGFFSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew #"_"#suffix),
+class VLSEGFFSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVLSEGFF" #nf #"e" #eew #"_" #emul),
ReadVLDX, ReadVMask
]>;
// Strided Segment Loads and Stores
-class VLSSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVLSSEG" #nf #"e" #eew #"_"#suffix),
+class VLSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVLSSEG" #nf #"e" #eew #"_" #emul),
ReadVLDX, ReadVLDSX, ReadVMask
]>;
-class VSSSEGSched<int nf, int eew, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVSSSEG" #nf #"e" #eew #"_"#suffix),
- !cast<SchedReadWrite>("ReadVSTS" #eew #"V_"#suffix),
+class VSSSEGSched<int nf, int eew, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul),
+ !cast<SchedReadWrite>("ReadVSTS" #eew #"V_" #emul),
ReadVSTX, ReadVSTSX, ReadVMask
]>;
// Indexed Segment Loads and Stores
-class VLXSEGSched<int nf, int eew, string o, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVL" #o #"XSEG" #nf #"e" #eew #"_"#suffix),
- ReadVLDX, !cast<SchedReadWrite>("ReadVLD" #o #"XV" #"_"#suffix), ReadVMask
+class VLXSEGSched<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVL" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
+ ReadVLDX, !cast<SchedReadWrite>("ReadVLD" #isOrdered #"XV_" #emul), ReadVMask
]>;
-class VSXSEGSched<int nf, int eew, string o, string suffix = "WorstCase"> : Sched<[
- !cast<SchedReadWrite>("WriteVS" #o #"XSEG" #nf #"e" #eew #"_"#suffix),
- !cast<SchedReadWrite>("ReadVST" #o #"X" #eew # "_"#suffix),
- ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV" # "_"#suffix), ReadVMask
+class VSXSEGSched<int nf, int eew, string isOrdered, string emul = "WorstCase"> : Sched<[
+ !cast<SchedReadWrite>("WriteVS" #isOrdered #"XSEG" #nf #"e" #eew #"_" #emul),
+ !cast<SchedReadWrite>("ReadVST" #isOrdered #"X" #eew #"_" #emul),
+ ReadVSTX, !cast<SchedReadWrite>("ReadVST" #isOrdered #"XV_" #emul), ReadVMask
]>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index b145178a24042..6e57e3a0466ab 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1728,31 +1728,32 @@ multiclass VPseudoSLoad {
}
multiclass VPseudoILoad<bit Ordered> {
- foreach eew = EEWList in {
- foreach sew = EEWList in {
- foreach lmul = MxSet<sew>.m in {
- defvar octuple_lmul = lmul.octuple;
+ foreach idxEEW = EEWList in {
+ foreach dataEEW = EEWList in {
+ foreach dataEMUL = MxSet<dataEEW>.m in {
+ defvar dataEMULOctuple = dataEMUL.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
- if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar DataLInfo = lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
- defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
- defvar Vreg = lmul.vrclass;
- defvar IdxVreg = idx_lmul.vrclass;
- defvar HasConstraint = !ne(sew, eew);
+ defvar idxEMULOctuple =
+ !srl(!mul(idxEEW, dataEMULOctuple), log2<dataEEW>.val);
+ if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
+ defvar DataLInfo = dataEMUL.MX;
+ defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
+ defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
+ defvar Vreg = dataEMUL.vrclass;
+ defvar IdxVreg = idxEMUL.vrclass;
+ defvar HasConstraint = !ne(dataEEW, idxEEW);
defvar Order = !if(Ordered, "O", "U");
- let VLMul = lmul.value in {
- def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
- VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
- VLXSched<eew, Order, DataLInfo, IdxLInfo>;
- def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_TU":
- VPseudoILoadNoMaskTU<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
- VLXSched<eew, Order, DataLInfo, IdxLInfo>;
- def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
- VPseudoILoadMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
+ let VLMul = dataEMUL.value in {
+ def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
+ VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
+ VLXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+ def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_TU":
+ VPseudoILoadNoMaskTU<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
+ VLXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+ def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
+ VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
- VLXSched<eew, Order, DataLInfo, IdxLInfo>;
+ VLXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
}
}
}
@@ -1802,26 +1803,27 @@ multiclass VPseudoSStore {
}
multiclass VPseudoIStore<bit Ordered> {
- foreach eew = EEWList in {
- foreach sew = EEWList in {
- foreach lmul = MxSet<sew>.m in {
- defvar octuple_lmul = lmul.octuple;
+ foreach idxEEW = EEWList in {
+ foreach dataEEW = EEWList in {
+ foreach dataEMUL = MxSet<dataEEW>.m in {
+ defvar dataEMULOctuple = dataEMUL.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
- if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar DataLInfo = lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
- defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
- defvar Vreg = lmul.vrclass;
- defvar IdxVreg = idx_lmul.vrclass;
+ defvar idxEMULOctuple =
+ !srl(!mul(idxEEW, dataEMULOctuple), log2<dataEEW>.val);
+ if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
+ defvar DataLInfo = dataEMUL.MX;
+ defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
+ defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
+ defvar Vreg = dataEMUL.vrclass;
+ defvar IdxVreg = idxEMUL.vrclass;
defvar Order = !if(Ordered, "O", "U");
- let VLMul = lmul.value in {
- def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
- VPseudoIStoreNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>,
- VSXSched<eew, Order, DataLInfo, IdxLInfo>;
- def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
- VPseudoIStoreMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>,
- VSXSched<eew, Order, DataLInfo, IdxLInfo>;
+ let VLMul = dataEMUL.value in {
+ def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
+ VPseudoIStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
+ VSXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
+ def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
+ VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
+ VSXSched<idxEEW, Order, DataLInfo, IdxLInfo>;
}
}
}
@@ -2058,11 +2060,11 @@ multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
foreach sew = EEWList in {
- defvar octuple_lmul = m.octuple;
+ defvar dataEMULOctuple = m.octuple;
// emul = lmul * eew / sew
- defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2<sew>.val);
- if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar emulMX = octuple_to_str<octuple_emul>.ret;
+ defvar idxEMULOctuple = !srl(!mul(dataEMULOctuple, eew), log2<sew>.val);
+ if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
+ defvar emulMX = octuple_to_str<idxEMULOctuple>.ret;
defvar emul = !cast<LMULInfo>("V_" # emulMX);
defvar sews = SchedSEWSet<mx>.val;
foreach e = sews in {
@@ -3752,34 +3754,34 @@ multiclass VPseudoSSegLoad {
}
multiclass VPseudoISegLoad<bit Ordered> {
- foreach idx_eew = EEWList in {
- foreach sew = EEWList in {
- foreach val_lmul = MxSet<sew>.m in {
- defvar octuple_lmul = val_lmul.octuple;
+ foreach idxEEW = EEWList in {
+ foreach dataEEW = EEWList in {
+ foreach dataEMUL = MxSet<dataEEW>.m in {
+ defvar dataEMULOctuple = dataEMUL.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2<sew>.val);
- if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar ValLInfo = val_lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
- defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
- defvar Vreg = val_lmul.vrclass;
- defvar IdxVreg = idx_lmul.vrclass;
+ defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), log2<dataEEW>.val);
+ if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
+ defvar DataLInfo = dataEMUL.MX;
+ defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
+ defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
+ defvar DataVreg = dataEMUL.vrclass;
+ defvar IdxVreg = idxEMUL.vrclass;
defvar Order = !if(Ordered, "O", "U");
- let VLMul = val_lmul.value in {
- foreach nf = NFSet<val_lmul>.L in {
- defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
- def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
- VPseudoISegLoadNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
+ let VLMul = dataEMUL.value in {
+ foreach nf = NFSet<dataEMUL>.L in {
+ defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
+ def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
+ VPseudoISegLoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
nf, Ordered>,
- VLXSEGSched<nf, idx_eew, Order, ValLInfo>;
- def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_TU" :
- VPseudoISegLoadNoMaskTU<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
+ VLXSEGSched<nf, idxEEW, Order, DataLInfo>;
+ def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_TU" :
+ VPseudoISegLoadNoMaskTU<Vreg, IdxVreg, idxEEW, idxEMUL.value,
nf, Ordered>,
- VLXSEGSched<nf, idx_eew, Order, ValLInfo>;
- def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
- VPseudoISegLoadMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
+ VLXSEGSched<nf, idxEEW, Order, DataLInfo>;
+ def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
+ VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
nf, Ordered>,
- VLXSEGSched<nf, idx_eew, Order, ValLInfo>;
+ VLXSEGSched<nf, idxEEW, Order, DataLInfo>;
}
}
}
@@ -3823,30 +3825,30 @@ multiclass VPseudoSSegStore {
}
multiclass VPseudoISegStore<bit Ordered> {
- foreach idx_eew = EEWList in {
- foreach sew = EEWList in {
- foreach val_lmul = MxSet<sew>.m in {
- defvar octuple_lmul = val_lmul.octuple;
+ foreach idxEEW = EEWList in {
+ foreach dataEEW = EEWList in {
+ foreach dataEMUL = MxSet<dataEEW>.m in {
+ defvar dataEMULOctuple = dataEMUL.octuple;
// Calculate emul = eew * lmul / sew
- defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2<sew>.val);
- if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
- defvar ValLInfo = val_lmul.MX;
- defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
- defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
- defvar Vreg = val_lmul.vrclass;
- defvar IdxVreg = idx_lmul.vrclass;
+ defvar idxEMULOctuple = !srl(!mul(idxEEW, dataEMULOctuple), log2<dataEEW>.val);
+ if !and(!ge(idxEMULOctuple, 1), !le(idxEMULOctuple, 64)) then {
+ defvar DataLInfo = dataEMUL.MX;
+ defvar IdxLInfo = octuple_to_str<idxEMULOctuple>.ret;
+ defvar idxEMUL = !cast<LMULInfo>("V_" # IdxLInfo);
+ defvar DataVreg = dataEMUL.vrclass;
+ defvar IdxVreg = idxEMUL.vrclass;
defvar Order = !if(Ordered, "O", "U");
- let VLMul = val_lmul.value in {
- foreach nf = NFSet<val_lmul>.L in {
- defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
- def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
- VPseudoISegStoreNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
+ let VLMul = dataEMUL.value in {
+ foreach nf = NFSet<dataEMUL>.L in {
+ defvar Vreg = SegRegClass<dataEMUL, nf>.RC;
+ def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
+ VPseudoISegStoreNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
nf, Ordered>,
- VSXSEGSched<nf, idx_eew, Order, ValLInfo>;
- def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
- VPseudoISegStoreMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value,
+ VSXSEGSched<nf, idxEEW, Order, DataLInfo>;
+ def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
+ VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
nf, Ordered>,
- VSXSEGSched<nf, idx_eew, Order, ValLInfo>;
+ VSXSEGSched<nf, idxEEW, Order, DataLInfo>;
}
}
}
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