[llvm] 8e26a90 - InstCombine: Add some baseline tests for recognizing fcmp as is.fpclass
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 21 05:15:12 PDT 2023
Author: Matt Arsenault
Date: 2023-04-21T08:15:03-04:00
New Revision: 8e26a9029c918c71d9f7966262fcce81d1f0d586
URL: https://github.com/llvm/llvm-project/commit/8e26a9029c918c71d9f7966262fcce81d1f0d586
DIFF: https://github.com/llvm/llvm-project/commit/8e26a9029c918c71d9f7966262fcce81d1f0d586.diff
LOG: InstCombine: Add some baseline tests for recognizing fcmp as is.fpclass
We should be able to recognize > 0, < 0 indicates the sign.
Added:
Modified:
llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
index cd69bc83c652..62d87b41e78b 100644
--- a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
+++ b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
@@ -1906,6 +1906,331 @@ define i1 @issubnormal_and_ninf_nnan_logical_select(half %x) {
ret i1 %class
}
+define i1 @fcmp_ueq_neginf_or_oge_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xHFC00
+ %cmp.oge.zero = fcmp oge half %x, 0xH0000
+ %class = or i1 %cmp.oge.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_neginf_or_oge_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xHFC00
+ %cmp.oge.zero = fcmp oge half %x, 0xH0000
+ %class = or i1 %cmp.oge.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_neginf_or_oge_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xHFC00
+ %cmp.oge.zero = fcmp oge half %x, 0xH0000
+ %class = or i1 %cmp.oge.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_neginf_or_oge_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xHFC00
+ %cmp.oge.zero = fcmp oge half %x, 0xH0000
+ %class = or i1 %cmp.oge.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_neginf_or_ogt_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xHFC00
+ %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
+ %class = or i1 %cmp.ogt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_neginf_or_ogt_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xHFC00
+ %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
+ %class = or i1 %cmp.ogt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xHFC00
+ %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
+ %class = or i1 %cmp.ogt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xHFC00
+ %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
+ %class = or i1 %cmp.ogt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_neginf_or_ugt_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xHFC00
+ %cmp.ugt.zero = fcmp ugt half %x, 0xH0000
+ %class = or i1 %cmp.ugt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_ueq_neginf_or_ugt_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xHFC00
+ %cmp.ugt.zero = fcmp ugt half %x, 0xH0000
+ %class = or i1 %cmp.ugt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
+; CHECK-NEXT: [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xHFC00
+ %cmp.ugt.zero = fcmp ugt half %x, 0xH0000
+ %class = or i1 %cmp.ugt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_posinf_or_ole_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xH7C00
+ %cmp.ole.zero = fcmp ole half %x, 0xH0000
+ %class = or i1 %cmp.ole.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_posinf_or_ole_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xH7C00
+ %cmp.ole.zero = fcmp ole half %x, 0xH0000
+ %class = or i1 %cmp.ole.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_posinf_or_ole_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xH7C00
+ %cmp.ole.zero = fcmp ole half %x, 0xH0000
+ %class = or i1 %cmp.ole.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_posinf_or_ole_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xH7C00
+ %cmp.ole.zero = fcmp ole half %x, 0xH0000
+ %class = or i1 %cmp.ole.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_posinf_or_olt_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xH7C00
+ %cmp.olt.zero = fcmp olt half %x, 0xH0000
+ %class = or i1 %cmp.olt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_posinf_or_olt_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xH7C00
+ %cmp.olt.zero = fcmp olt half %x, 0xH0000
+ %class = or i1 %cmp.olt.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_posinf_or_ult_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xH7C00
+ %cmp.ult.zero = fcmp ult half %x, 0xH0000
+ %class = or i1 %cmp.ult.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_posinf_or_ult_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xH7C00
+ %cmp.ult.zero = fcmp ult half %x, 0xH0000
+ %class = or i1 %cmp.ult.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_posinf_or_ult_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xH7C00
+ %cmp.ult.zero = fcmp ult half %x, 0xH0000
+ %class = or i1 %cmp.ult.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_posinf_or_ult_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xH7C00
+ %cmp.ult.zero = fcmp ult half %x, 0xH0000
+ %class = or i1 %cmp.ult.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_posinf_or_ule_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xH7C00
+ %cmp.ule.zero = fcmp ule half %x, 0xH0000
+ %class = or i1 %cmp.ule.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_posinf_or_ule_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xH7C00
+ %cmp.ule.zero = fcmp ule half %x, 0xH0000
+ %class = or i1 %cmp.ule.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_oeq_posinf_or_ule_zero_f16_daz(half %x) #1 {
+; CHECK-LABEL: @fcmp_oeq_posinf_or_ule_zero_f16_daz(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp oeq half %x, 0xH7C00
+ %cmp.ule.zero = fcmp ule half %x, 0xH0000
+ %class = or i1 %cmp.ule.zero, %cmpinf
+ ret i1 %class
+}
+
+define i1 @fcmp_ueq_posinf_or_olt_zero_f16(half %x) {
+; CHECK-LABEL: @fcmp_ueq_posinf_or_olt_zero_f16(
+; CHECK-NEXT: [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
+; CHECK-NEXT: [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
+; CHECK-NEXT: [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %cmpinf = fcmp ueq half %x, 0xH7C00
+ %cmp.olt.zero = fcmp olt half %x, 0xH0000
+ %class = or i1 %cmp.olt.zero, %cmpinf
+ ret i1 %class
+}
+
declare half @llvm.fabs.f16(half) #0
declare half @llvm.canonicalize.f16(half) #0
declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #0
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