[llvm] aab0ca3 - Fix uninitialized scalar members in CodeGen
Akshay Khadse via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 20 21:22:47 PDT 2023
Author: Akshay Khadse
Date: 2023-04-21T12:22:34+08:00
New Revision: aab0ca3e794a212a2ac0a24a4a1a9ed18ad06267
URL: https://github.com/llvm/llvm-project/commit/aab0ca3e794a212a2ac0a24a4a1a9ed18ad06267
DIFF: https://github.com/llvm/llvm-project/commit/aab0ca3e794a212a2ac0a24a4a1a9ed18ad06267.diff
LOG: Fix uninitialized scalar members in CodeGen
This change fixes some static code analysis warnings.
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D148811
Added:
Modified:
llvm/include/llvm/CodeGen/AccelTable.h
llvm/include/llvm/CodeGen/MachineModuleInfo.h
llvm/include/llvm/CodeGen/MachinePipeliner.h
llvm/include/llvm/CodeGen/RegisterPressure.h
llvm/include/llvm/CodeGen/ScheduleDAG.h
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/include/llvm/CodeGen/TileShapeInfo.h
llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp
llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
llvm/lib/CodeGen/GlobalMerge.cpp
llvm/lib/CodeGen/InterleavedAccessPass.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/lib/CodeGen/SplitKit.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/AccelTable.h b/llvm/include/llvm/CodeGen/AccelTable.h
index be7ed03deb27f..46537c9cb6815 100644
--- a/llvm/include/llvm/CodeGen/AccelTable.h
+++ b/llvm/include/llvm/CodeGen/AccelTable.h
@@ -161,8 +161,8 @@ class AccelTableBase {
StringEntries Entries;
HashFn *Hash;
- uint32_t BucketCount;
- uint32_t UniqueHashCount;
+ uint32_t BucketCount = 0;
+ uint32_t UniqueHashCount = 0;
HashList Hashes;
BucketList Buckets;
diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h
index d774653c6ed18..4f0ada3d7e17a 100644
--- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h
@@ -95,7 +95,7 @@ class MachineModuleInfo {
/// \{
/// The current call site index being processed, if any. 0 if none.
- unsigned CurCallSite;
+ unsigned CurCallSite = 0;
/// \}
@@ -106,11 +106,11 @@ class MachineModuleInfo {
// go into .eh_frame only, while others go into .debug_frame only.
/// True if debugging information is available in this module.
- bool DbgInfoAvailable;
+ bool DbgInfoAvailable = false;
/// True if this module is being built for windows/msvc, and uses floating
/// point. This is used to emit an undefined reference to _fltused.
- bool UsesMSVCFloatingPoint;
+ bool UsesMSVCFloatingPoint = false;
/// Maps IR Functions to their corresponding MachineFunctions.
DenseMap<const Function*, std::unique_ptr<MachineFunction>> MachineFunctions;
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index 3833d80f503ab..fb9dd0732d253 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -168,7 +168,7 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
SmallVector<SmallVector<int, 4>, 16> AdjK;
// Node to Index from ScheduleDAGTopologicalSort
std::vector<int> *Node2Idx;
- unsigned NumPaths;
+ unsigned NumPaths = 0u;
static unsigned MaxPaths;
public:
@@ -464,7 +464,7 @@ class ResourceManager {
/// processor resource masks. There is exactly one element per each processor
/// resource declared by the scheduling model.
llvm::SmallVector<uint64_t, DefaultProcResSize> ProcResourceMasks;
- int InitiationInterval;
+ int InitiationInterval = 0;
/// The number of micro operations that can be scheduled at a cycle.
int IssueWidth;
diff --git a/llvm/include/llvm/CodeGen/RegisterPressure.h b/llvm/include/llvm/CodeGen/RegisterPressure.h
index 6fa19c50c6c8c..2d08401261709 100644
--- a/llvm/include/llvm/CodeGen/RegisterPressure.h
+++ b/llvm/include/llvm/CodeGen/RegisterPressure.h
@@ -272,7 +272,7 @@ class LiveRegSet {
using RegSet = SparseSet<IndexMaskPair>;
RegSet Regs;
- unsigned NumRegUnits;
+ unsigned NumRegUnits = 0u;
unsigned getSparseIndexFromReg(Register Reg) const {
if (Reg.isVirtual())
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 2fe2aabe833e7..50fff79d26236 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -93,7 +93,7 @@ class TargetRegisterInfo;
/// The time associated with this edge. Often this is just the value of the
/// Latency field of the predecessor, however advanced models may provide
/// additional information about specific edges.
- unsigned Latency;
+ unsigned Latency = 0u;
public:
/// Constructs a null SDep. This is only for use by container classes which
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 920562a9caed6..620fdfc9f754d 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -470,7 +470,7 @@ class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
/// We do not place that under `#if LLVM_ENABLE_ABI_BREAKING_CHECKS`
/// intentionally because it adds unneeded complexity without noticeable
/// benefits (see discussion with @thakis in D120714).
- uint16_t PersistentId;
+ uint16_t PersistentId = 0xffff;
protected:
// We define a set of mini-helper classes to help us interpret the bits in our
diff --git a/llvm/include/llvm/CodeGen/TileShapeInfo.h b/llvm/include/llvm/CodeGen/TileShapeInfo.h
index 1b5f902139fbf..48c2d9ae70dfa 100644
--- a/llvm/include/llvm/CodeGen/TileShapeInfo.h
+++ b/llvm/include/llvm/CodeGen/TileShapeInfo.h
@@ -87,8 +87,8 @@ class ShapeT {
static constexpr int64_t InvalidImmShape = -1;
MachineOperand *Row;
MachineOperand *Col;
- int64_t RowImm;
- int64_t ColImm;
+ int64_t RowImm = -1;
+ int64_t ColImm = -1;
};
} // namespace llvm
diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp
index 22ecc51997423..a533551f4b474 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp
@@ -194,8 +194,8 @@ class Dwarf5AccelTableWriter : public AccelTableWriter {
uint32_t CompUnitCount;
uint32_t LocalTypeUnitCount = 0;
uint32_t ForeignTypeUnitCount = 0;
- uint32_t BucketCount;
- uint32_t NameCount;
+ uint32_t BucketCount = 0;
+ uint32_t NameCount = 0;
uint32_t AbbrevTableSize = 0;
uint32_t AugmentationStringSize = sizeof(AugmentationString);
char AugmentationString[8] = {'L', 'L', 'V', 'M', '0', '7', '0', '0'};
diff --git a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
index 3cfe935e2cca3..b7fc502b9a2ee 100644
--- a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
+++ b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
@@ -137,7 +137,8 @@ struct ComplexDeinterleavingCompositeNode {
Instruction *Real;
Instruction *Imag;
- ComplexDeinterleavingRotation Rotation;
+ ComplexDeinterleavingRotation Rotation =
+ ComplexDeinterleavingRotation::Rotation_0;
SmallVector<RawNodePtr> Operands;
Value *ReplacementNode = nullptr;
diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp
index ff157f326c572..f259cbc1d788e 100644
--- a/llvm/lib/CodeGen/GlobalMerge.cpp
+++ b/llvm/lib/CodeGen/GlobalMerge.cpp
@@ -156,7 +156,7 @@ namespace {
/// Whether we should merge global variables that have external linkage.
bool MergeExternalGlobals = false;
- bool IsMachO;
+ bool IsMachO = false;
bool doMerge(SmallVectorImpl<GlobalVariable*> &Globals,
Module &M, bool isConst, unsigned AddrSpace) const;
diff --git a/llvm/lib/CodeGen/InterleavedAccessPass.cpp b/llvm/lib/CodeGen/InterleavedAccessPass.cpp
index a65fafc4d2db1..e4f581f2b0629 100644
--- a/llvm/lib/CodeGen/InterleavedAccessPass.cpp
+++ b/llvm/lib/CodeGen/InterleavedAccessPass.cpp
@@ -103,7 +103,7 @@ class InterleavedAccess : public FunctionPass {
const TargetLowering *TLI = nullptr;
/// The maximum supported interleave factor.
- unsigned MaxFactor;
+ unsigned MaxFactor = 0u;
/// Transform an interleaved load into target specific intrinsics.
bool lowerInterleavedLoad(LoadInst *LI,
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 2d93adea6b9bc..5b01743d23e0a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -69,7 +69,7 @@ class ScheduleDAGFast : public ScheduleDAGSDNodes {
/// LiveRegDefs - A set of physical registers and their definition
/// that are "live". These nodes must be scheduled before any other nodes that
/// modifies the registers can be scheduled.
- unsigned NumLiveRegs;
+ unsigned NumLiveRegs = 0u;
std::vector<SUnit*> LiveRegDefs;
std::vector<unsigned> LiveRegCycles;
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 31b2f3f5de601..78ac0c27d7205 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -156,16 +156,16 @@ class ScheduleDAGRRList : public ScheduleDAGSDNodes {
unsigned CurCycle = 0;
/// MinAvailableCycle - Cycle of the soonest available instruction.
- unsigned MinAvailableCycle;
+ unsigned MinAvailableCycle = ~0u;
/// IssueCount - Count instructions issued in this cycle
/// Currently valid only for bottom-up scheduling.
- unsigned IssueCount;
+ unsigned IssueCount = 0u;
/// LiveRegDefs - A set of physical registers and their definition
/// that are "live". These nodes must be scheduled before any other nodes that
/// modifies the registers can be scheduled.
- unsigned NumLiveRegs;
+ unsigned NumLiveRegs = 0u;
std::unique_ptr<SUnit*[]> LiveRegDefs;
std::unique_ptr<SUnit*[]> LiveRegGens;
diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/lib/CodeGen/SplitKit.h
index 5a3428a5e91f9..f764ffd4750cc 100644
--- a/llvm/lib/CodeGen/SplitKit.h
+++ b/llvm/lib/CodeGen/SplitKit.h
@@ -151,13 +151,13 @@ class LLVM_LIBRARY_VISIBILITY SplitAnalysis {
/// NumGapBlocks - Number of duplicate entries in UseBlocks for blocks where
/// the live range has a gap.
- unsigned NumGapBlocks;
+ unsigned NumGapBlocks = 0u;
/// ThroughBlocks - Block numbers where CurLI is live through without uses.
BitVector ThroughBlocks;
/// NumThroughBlocks - Number of live-through blocks.
- unsigned NumThroughBlocks;
+ unsigned NumThroughBlocks = 0u;
// Sumarize statistics by counting instructions using CurLI.
void analyzeUses();
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