[PATCH] D148856: [M68k] Override `CanLowerReturn` to fix assertion with large return

[Ian D. Scott via Phabricator via llvm-commits]

ids1024 created this revision.
ids1024 added a reviewer: myhsu.
Herald added subscribers: JDevlieghere, hiraditya.
Herald added a project: All.
ids1024 requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

If it couldn't fit the return value in two registers, this caused an error during codegen. It seems this method is implemented in other backends but not here, and allows it to pass return values in memory when it isn't able to do so in registers.

Seems to fix compilation of Rust code with certain return types: https://github.com/rust-lang/rust/issues/89498


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148856

Files:
  llvm/lib/Target/M68k/M68kISelLowering.cpp
  llvm/lib/Target/M68k/M68kISelLowering.h
  llvm/test/CodeGen/M68k/multiple-return.ll


Index: llvm/test/CodeGen/M68k/multiple-return.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/M68k/multiple-return.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
+
+define { i32, i32, i32, i32 } @test() {
+; CHECK-LABEL: test:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %start
+; CHECK-NEXT:    move.l (4,%sp), %a0
+; CHECK-NEXT:    move.l #23, (12,%a0)
+; CHECK-NEXT:    move.l #19, (8,%a0)
+; CHECK-NEXT:    move.l #17, (4,%a0)
+; CHECK-NEXT:    move.l #13, (%a0)
+; CHECK-NEXT:    move.l %a0, %d0
+; CHECK-NEXT:    move.l (%sp), %a1
+; CHECK-NEXT:    adda.l #4, %sp
+; CHECK-NEXT:    move.l %a1, (%sp)
+; CHECK-NEXT:    rts
+start:
+  ret { i32, i32, i32, i32 } { i32 13, i32 17, i32 19, i32 23 }
+}
Index: llvm/lib/Target/M68k/M68kISelLowering.h
===================================================================
--- llvm/lib/Target/M68k/M68kISelLowering.h
+++ llvm/lib/Target/M68k/M68kISelLowering.h
@@ -257,6 +257,11 @@
   SDValue LowerCall(CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;
 
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool isVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
+
   /// Lower the result values of a call into the
   /// appropriate copies out of appropriate physical registers.
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
Index: llvm/lib/Target/M68k/M68kISelLowering.cpp
===================================================================
--- llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -1058,6 +1058,16 @@
 //              Return Value Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+bool
+M68kTargetLowering::CanLowerReturn(CallingConv::ID CCID,
+                                   MachineFunction &MF, bool IsVarArg,
+                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
+                                   LLVMContext &Context) const {
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context);
+  return CCInfo.CheckReturn(Outs, RetCC_M68k);
+}
+
 SDValue
 M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
                                 bool IsVarArg,


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D148856.515519.patch
Type: text/x-patch
Size: 2614 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230420/313450ef/attachment.bin>