[PATCH] D148824: AMDGPU: Define sub-class of SGPR_64 for tail call return

[Changpeng Fang via Phabricator via llvm-commits]

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  Registers for tail call return should not be clobbered by callee.

So we need a sub-class of SGPR_64 (excluding callee saved registers (CSR)) to hold
the tail call return address.

Because GFX and C calling conventions have different CSR, we need to define 
 the sub-class separately. This work is an extension of D147096 <https://reviews.llvm.org/D147096> with the 
 consideration of GFX calling convention.

Based on the calling conventions, different instructions will be selected with
 different sub-class of SGPR_64 as the input.


https://reviews.llvm.org/D148824

Files:
  llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
  llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
  llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
  llvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll

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