[llvm] 328cfa8 - [RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 20 10:00:47 PDT 2023
Author: Craig Topper
Date: 2023-04-20T10:00:30-07:00
New Revision: 328cfa840d791deeed84aa4e2fda93d591bfb8d7
URL: https://github.com/llvm/llvm-project/commit/328cfa840d791deeed84aa4e2fda93d591bfb8d7
DIFF: https://github.com/llvm/llvm-project/commit/328cfa840d791deeed84aa4e2fda93d591bfb8d7.diff
LOG: [RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget
This adds an option to emit the command line -mattr/-march into the
attributes of an object file. This can be useful to get objdump to
disassemble instructions that aren't in the base without forcing
users to add a .attribute to the assembly file.
The binutils assembler does this by default.
Similar option exists for ARM. I will wire it to a clang option in
another patch. Similar to https://reviews.llvm.org/D31813
Reviewed By: asb, kito-cheng
Differential Revision: https://reviews.llvm.org/D148782
Added:
llvm/test/MC/RISCV/default-build-attributes.s
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/test/MC/RISCV/attribute.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index e930bb6d21e41..df7947f2d8818 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -35,6 +35,7 @@
#include "llvm/MC/MCValue.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/RISCVAttributes.h"
#include "llvm/Support/RISCVISAInfo.h"
@@ -48,6 +49,9 @@ using namespace llvm;
STATISTIC(RISCVNumInstrsCompressed,
"Number of RISC-V Compressed instructions emitted");
+static cl::opt<bool> AddBuildAttributes("riscv-add-build-attributes",
+ cl::init(false));
+
namespace llvm {
extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
} // namespace llvm
@@ -240,6 +244,8 @@ class RISCVAsmParser : public MCTargetAsmParser {
RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI, MII) {
+ MCAsmParserExtension::Initialize(Parser);
+
Parser.addAliasForDirective(".half", ".2byte");
Parser.addAliasForDirective(".hword", ".2byte");
Parser.addAliasForDirective(".word", ".4byte");
@@ -265,6 +271,9 @@ class RISCVAsmParser : public MCTargetAsmParser {
const MCObjectFileInfo *MOFI = Parser.getContext().getObjectFileInfo();
ParserOptions.IsPicEnabled = MOFI->isPositionIndependent();
+
+ if (AddBuildAttributes)
+ getTargetStreamer().emitTargetAttributes(STI, /*EmitStackAlign*/ false);
}
};
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index 7e47be0caf3aa..93c1a1fc2e81a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -46,11 +46,13 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
TargetABI = ABI;
}
-void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
+void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
+ bool EmitStackAlign) {
if (STI.hasFeature(RISCV::FeatureRVE))
report_fatal_error("Codegen not yet implemented for RVE");
- emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
+ if (EmitStackAlign)
+ emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
auto ParseResult = RISCVFeatures::parseFeatureBits(
STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index f3b20de4328db..8298f5e6c051f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -40,7 +40,7 @@ class RISCVTargetStreamer : public MCTargetStreamer {
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
StringRef StringValue);
- void emitTargetAttributes(const MCSubtargetInfo &STI);
+ void emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign);
void setTargetABI(RISCVABI::ABI ABI);
RISCVABI::ABI getTargetABI() const { return TargetABI; }
};
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index b2dedc1103134..efb45ea5ac01e 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -229,7 +229,7 @@ void RISCVAsmPrinter::emitAttributes() {
// Use MCSubtargetInfo from TargetMachine. Individual functions may have
// attributes that
diff er from other functions in the module and we have no
// way to know which function is correct.
- RTS.emitTargetAttributes(*TM.getMCSubtargetInfo());
+ RTS.emitTargetAttributes(*TM.getMCSubtargetInfo(), /*EmitStackAlign*/ true);
}
void RISCVAsmPrinter::emitFunctionEntryLabel() {
diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s
index d36fdd18bdd9c..56f0cb1daf176 100644
--- a/llvm/test/MC/RISCV/attribute.s
+++ b/llvm/test/MC/RISCV/attribute.s
@@ -2,6 +2,10 @@
# RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
# RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv32 -filetype=asm -riscv-add-build-attributes \
+# RUN: | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm -riscv-add-build-attributes \
+# RUN: | FileCheck %s
.attribute stack_align, 16
# CHECK: attribute 4, 16
diff --git a/llvm/test/MC/RISCV/default-build-attributes.s b/llvm/test/MC/RISCV/default-build-attributes.s
new file mode 100644
index 0000000000000..3f96ca0a46c42
--- /dev/null
+++ b/llvm/test/MC/RISCV/default-build-attributes.s
@@ -0,0 +1,20 @@
+# RUN: llvm-mc %s -triple=riscv32 -filetype=asm -riscv-add-build-attributes \
+# RUN: | FileCheck %s --check-prefixes=RV32
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm -riscv-add-build-attributes \
+# RUN: | FileCheck %s --check-prefixes=RV64
+# RUN: llvm-mc %s -triple=riscv32 -filetype=asm -riscv-add-build-attributes \
+# RUN: -mattr=+m | FileCheck %s --check-prefixes=RV32M
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm -riscv-add-build-attributes \
+# RUN: -mattr=+m | FileCheck %s --check-prefixes=RV64M
+
+# RV32-NOT: attribute 4
+# RV32: attribute 5, "rv32i2p1"
+
+# RV64-NOT: attribute 4
+# RV64: attribute 5, "rv64i2p1"
+
+# RV32M-NOT: attribute 4
+# RV32M: attribute 5, "rv32i2p1_m2p0"
+
+# RV64M-NOT: attribute 4
+# RV64M: attribute 5, "rv64i2p1_m2p0"
More information about the llvm-commits
mailing list