[llvm] 3794428 - [AArch64] Additional hadd/rhadd tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 20 09:51:58 PDT 2023
Author: David Green
Date: 2023-04-20T17:51:54+01:00
New Revision: 3794428f0a4c15cc5cd7b95aeb1e9d695e4af416
URL: https://github.com/llvm/llvm-project/commit/3794428f0a4c15cc5cd7b95aeb1e9d695e4af416
DIFF: https://github.com/llvm/llvm-project/commit/3794428f0a4c15cc5cd7b95aeb1e9d695e4af416.diff
LOG: [AArch64] Additional hadd/rhadd tests. NFC
See D148809
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-vhadd.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
index cab2ed035d86..fdd4be30dbc8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
@@ -867,6 +867,213 @@ define <4 x i16> @hadd8_zext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
ret <4 x i16> %resulti8
}
+define <2 x i16> @hadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: hadd8x2_sext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #24
+; CHECK-NEXT: shl.2s v1, v1, #24
+; CHECK-NEXT: sshr.2s v0, v0, #24
+; CHECK-NEXT: sshr.2s v1, v1, #24
+; CHECK-NEXT: shadd.2s v0, v0, v1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
+ %add = add nsw <2 x i16> %zextsrc1, %zextsrc2
+ %resulti8 = ashr <2 x i16> %add, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+define <2 x i16> @hadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: hadd8x2_zext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-NEXT: and.8b v0, v0, v2
+; CHECK-NEXT: and.8b v1, v1, v2
+; CHECK-NEXT: uhadd.2s v0, v0, v1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
+ %add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
+ %resulti8 = lshr <2 x i16> %add, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+define <2 x i16> @hadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: hadd8x2_sext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #24
+; CHECK-NEXT: shl.2s v1, v1, #24
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: sshr.2s v0, v0, #24
+; CHECK-NEXT: ssra.2s v0, v1, #24
+; CHECK-NEXT: and.8b v0, v0, v2
+; CHECK-NEXT: ushr.2s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
+ %add = add nsw <2 x i16> %zextsrc1, %zextsrc2
+ %resulti8 = lshr <2 x i16> %add, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+define <2 x i16> @hadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: hadd8x2_zext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-NEXT: and.8b v0, v0, v2
+; CHECK-NEXT: and.8b v1, v1, v2
+; CHECK-NEXT: uhadd.2s v0, v0, v1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
+ %add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
+ %resulti8 = lshr <2 x i16> %add, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+define <4 x i16> @rhadd8_sext_asr(<4 x i8> %src1, <4 x i8> %src2) {
+; CHECK-LABEL: rhadd8_sext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.4h v0, v0, #8
+; CHECK-NEXT: shl.4h v1, v1, #8
+; CHECK-NEXT: sshr.4h v0, v0, #8
+; CHECK-NEXT: sshr.4h v1, v1, #8
+; CHECK-NEXT: srhadd.4h v0, v0, v1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <4 x i8> %src1 to <4 x i16>
+ %zextsrc2 = sext <4 x i8> %src2 to <4 x i16>
+ %add = add nsw <4 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nsw <4 x i16> %add, <i16 1, i16 1, i16 1, i16 1>
+ %resulti8 = ashr <4 x i16> %add2, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %resulti8
+}
+
+define <4 x i16> @rhadd8_zext_asr(<4 x i8> %src1, <4 x i8> %src2) {
+; CHECK-LABEL: rhadd8_zext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-NEXT: urhadd.4h v0, v0, v1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <4 x i8> %src1 to <4 x i16>
+ %zextsrc2 = zext <4 x i8> %src2 to <4 x i16>
+ %add = add nuw nsw <4 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nuw nsw <4 x i16> %add, <i16 1, i16 1, i16 1, i16 1>
+ %resulti8 = lshr <4 x i16> %add2, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %resulti8
+}
+
+define <4 x i16> @rhadd8_sext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
+; CHECK-LABEL: rhadd8_sext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.4h v0, v0, #8
+; CHECK-NEXT: shl.4h v1, v1, #8
+; CHECK-NEXT: sshr.4h v0, v0, #8
+; CHECK-NEXT: sshr.4h v1, v1, #8
+; CHECK-NEXT: mvn.8b v0, v0
+; CHECK-NEXT: sub.4h v0, v1, v0
+; CHECK-NEXT: ushr.4h v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <4 x i8> %src1 to <4 x i16>
+ %zextsrc2 = sext <4 x i8> %src2 to <4 x i16>
+ %add = add nsw <4 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nsw <4 x i16> %add, <i16 1, i16 1, i16 1, i16 1>
+ %resulti8 = lshr <4 x i16> %add2, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %resulti8
+}
+
+define <4 x i16> @rhadd8_zext_lsr(<4 x i8> %src1, <4 x i8> %src2) {
+; CHECK-LABEL: rhadd8_zext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: bic.4h v0, #255, lsl #8
+; CHECK-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-NEXT: urhadd.4h v0, v0, v1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <4 x i8> %src1 to <4 x i16>
+ %zextsrc2 = zext <4 x i8> %src2 to <4 x i16>
+ %add = add nuw nsw <4 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nuw nsw <4 x i16> %add, <i16 1, i16 1, i16 1, i16 1>
+ %resulti8 = lshr <4 x i16> %add2, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %resulti8
+}
+
+define <2 x i16> @rhadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: rhadd8x2_sext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #24
+; CHECK-NEXT: shl.2s v1, v1, #24
+; CHECK-NEXT: sshr.2s v0, v0, #24
+; CHECK-NEXT: sshr.2s v1, v1, #24
+; CHECK-NEXT: mvn.8b v0, v0
+; CHECK-NEXT: sub.2s v0, v1, v0
+; CHECK-NEXT: sshr.2s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
+ %add = add nsw <2 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nsw <2 x i16> %add, <i16 1, i16 1>
+ %resulti8 = ashr <2 x i16> %add2, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+define <2 x i16> @rhadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: rhadd8x2_zext_asr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-NEXT: and.8b v0, v0, v2
+; CHECK-NEXT: and.8b v1, v1, v2
+; CHECK-NEXT: mvn.8b v0, v0
+; CHECK-NEXT: sub.2s v0, v1, v0
+; CHECK-NEXT: ushr.2s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
+ %add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nuw nsw <2 x i16> %add, <i16 1, i16 1>
+ %resulti8 = lshr <2 x i16> %add2, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+define <2 x i16> @rhadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: rhadd8x2_sext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: shl.2s v0, v0, #24
+; CHECK-NEXT: shl.2s v1, v1, #24
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: sshr.2s v0, v0, #24
+; CHECK-NEXT: sshr.2s v1, v1, #24
+; CHECK-NEXT: mvn.8b v0, v0
+; CHECK-NEXT: sub.2s v0, v1, v0
+; CHECK-NEXT: and.8b v0, v0, v2
+; CHECK-NEXT: ushr.2s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
+ %add = add nsw <2 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nsw <2 x i16> %add, <i16 1, i16 1>
+ %resulti8 = lshr <2 x i16> %add2, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+define <2 x i16> @rhadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
+; CHECK-LABEL: rhadd8x2_zext_lsr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x0000ff000000ff
+; CHECK-NEXT: and.8b v0, v0, v2
+; CHECK-NEXT: and.8b v1, v1, v2
+; CHECK-NEXT: mvn.8b v0, v0
+; CHECK-NEXT: sub.2s v0, v1, v0
+; CHECK-NEXT: ushr.2s v0, v0, #1
+; CHECK-NEXT: ret
+ %zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
+ %zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
+ %add = add nuw nsw <2 x i16> %zextsrc1, %zextsrc2
+ %add2 = add nuw nsw <2 x i16> %add, <i16 1, i16 1>
+ %resulti8 = lshr <2 x i16> %add2, <i16 1, i16 1>
+ ret <2 x i16> %resulti8
+}
+
+
define void @testLowerToSHADD8b_c(<8 x i8> %src1, ptr nocapture writeonly %dest) {
; CHECK-LABEL: testLowerToSHADD8b_c:
; CHECK: // %bb.0:
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