[PATCH] D148096: [AMDGPU][GlobalISel] Widen the vector operand in G_BUILD/INSERT/EXTRACT_VECTOR

[Mateja Marjanovic via Phabricator via llvm-commits]

matejam updated this revision to Diff 515334.
matejam added a comment.

This is an extension of https://reviews.llvm.org/D144198.
It includes checking the exact width in get*ClassForBitWidth and also widening of the vector operand of
G_BUILD_VECTOR, G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT instructions.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148096/new/

https://reviews.llvm.org/D148096

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

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