[PATCH] D148597: [PowerPC] Implement DFP add and sub instructions.

Stefan Pintilie via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 19 07:51:54 PDT 2023

stefanp added inline comments.

Comment at: llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp:120
+  assert((RegNo & 1) == 0 && "Expecting an even register number.");
+  return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
amyk wrote:
> I have a question that isn't directly related to your patch per se. I think what we do here makes sense to shift the RegNo by 1 for the even numbering. I noticed that the GPR pair implementation does not do this, and I was wondering if that is incorrect?
Yes, they are both correct.
The reason why I have to do a shift here is because I have to index into `FpRegs` while the GPR pair just indexes into `XRegs`. The `FpRegs` only contains the even registers and so I have to divide by two in order to get the correct register. For the `XRegs` all of the registers are present including the odd numbered ones and so they don't have to divide by two because they will have to skip over the odd numbered registers.  

  rG LLVM Github Monorepo



More information about the llvm-commits mailing list