[PATCH] D148523: [LegalizeTypes][VP] Widen fixed length vectors to VP nodes

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll:949
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT:    vdivu.vv v10, v11, v10
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
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craig.topper wrote:
> Can't we use a VL=6 vdivu.vv?
I think so, this patch just didn't handle the case for ops that can trap like udiv/urem etc.


Repository:
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  https://reviews.llvm.org/D148523/new/

https://reviews.llvm.org/D148523