[PATCH] D147712: [RISCV] Add tests for concats of vectors that could become strided loads
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 19 01:37:20 PDT 2023
This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd23de1bd155b: [RISCV] Add tests for concats of vectors that could become strided loads (authored by luke).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147712/new/
https://reviews.llvm.org/D147712
Files:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
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