[PATCH] D148686: [RISCV] Add scheduling for Zfa instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td:89
+            (ins loadfpimm:$imm), "fli.s", "$rd, $imm">,
+            Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
 
----------------
Reads are supposed to map to input register operands. There's no input register here.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td:97
+def FROUND_S : FPUnaryOp_r_frm<0b0100000, 0b00100, FPR32, FPR32, "fround.s">,
+               Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
+def FROUNDNX_S : FPUnaryOp_r_frm<0b0100000, 0b00101, FPR32, FPR32, "froundnx.s">,
----------------
This is f32->f32 why should it use the F64ToF32 sched class? Should probably add new classes.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148686/new/

https://reviews.llvm.org/D148686