[llvm] 522c7b1 - [RISCV][NFC] Consistently use Opcode local variable in RISCVAsmParser::validateInstruction

[Alex Bradbury via llvm-commits]

Author: Alex Bradbury
Date: 2023-04-19T06:31:10+01:00
New Revision: 522c7b1e76dac1f08f6bc675681b39fbd19796a9

URL: https://github.com/llvm/llvm-project/commit/522c7b1e76dac1f08f6bc675681b39fbd19796a9
DIFF: https://github.com/llvm/llvm-project/commit/522c7b1e76dac1f08f6bc675681b39fbd19796a9.diff

LOG: [RISCV][NFC] Consistently use Opcode local variable in RISCVAsmParser::validateInstruction

As we already do `unsigned Opcode = Inst.getOpcode();`, we may as well
use that variable.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index c29deb2ef4135..4f6d6d206d602 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2892,8 +2892,10 @@ std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultFRMArgOp() const {
 
 bool RISCVAsmParser::validateInstruction(MCInst &Inst,
                                          OperandVector &Operands) {
-  if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T ||
-      Inst.getOpcode() == RISCV::PseudoVMSGE_VX_M_T) {
+  unsigned Opcode = Inst.getOpcode();
+
+  if (Opcode == RISCV::PseudoVMSGEU_VX_M_T ||
+      Opcode == RISCV::PseudoVMSGE_VX_M_T) {
     unsigned DestReg = Inst.getOperand(0).getReg();
     unsigned TempReg = Inst.getOperand(1).getReg();
     if (DestReg == TempReg) {
@@ -2903,8 +2905,6 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
     }
   }
 
-  unsigned Opcode = Inst.getOpcode();
-
   if (Opcode == RISCV::TH_LDD || Opcode == RISCV::TH_LWUD ||
       Opcode == RISCV::TH_LWD) {
     unsigned Rd1 = Inst.getOperand(0).getReg();
@@ -2931,7 +2931,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
     return Error(Loc, "Operand must be constant 4.");
   }
 
-  const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
+  const MCInstrDesc &MCID = MII.get(Opcode);
   RISCVII::VConstraintType Constraints = RISCVII::getConstraint(MCID.TSFlags);
   if (Constraints == RISCVII::NoConstraint)
     return false;