[PATCH] D148519: [RISCV] Support vector strict rounding operations.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2583
+  }
+  SDValue BaseRes = DAG.getNode(BaseOpc, DL, VT, Src);
+  Chain = DAG.getMergeValues({Unorder.getValue(1), Fadd.getValue(1)}, DL);
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craig.topper wrote:
> I'm not sure we can convert to the base opcode. I think we need to keep the chain through the expanded opcodes. We need to make sure rounding mode changes or reads of fflags that should logically happen after the rounding expansion can't move up. The fadd probably protects anything above from sinking down.
Is the strict_nearbyint is the cause that we should not covert to base opcode? If some modification of FRM is after strict_nearbyint and we covert strict_nearbyint to nearbyint, it maybe let compiler move the modification of FRM before the nearbyint.


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  https://reviews.llvm.org/D148519/new/

https://reviews.llvm.org/D148519