[PATCH] D148185: Add more efficient bitwise vector reductions on AArch64

[Markus Everling via Phabricator via llvm-commits]

Sp00ph updated this revision to Diff 514790.
Sp00ph added a comment.

Use `sign_ext` before `umax/umin`. Using `any_ext` instead could lead to miscompilations similar to this: https://github.com/llvm/llvm-project/issues/62211 . Also, choose the best bit width to extend to for short i1 vectors. This leads to better codegen as it doesn't need to e.g. truncate setcc results as part of the reduction.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148185/new/

https://reviews.llvm.org/D148185

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
  llvm/test/CodeGen/AArch64/double_reduct.ll
  llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

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