[PATCH] D148597: [PowerPC] Implement DFP add and sub instructions.

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


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Comment at: llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp:120
+  assert((RegNo & 1) == 0 && "Expecting an even register number.");
+  return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
+}
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I have a question that isn't directly related to your patch per se. I think what we do here makes sense to shift the RegNo by 1 for the even numbering. I noticed that the GPR pair implementation does not do this, and I was wondering if that is incorrect?


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Comment at: llvm/lib/Target/PowerPC/PPCInstrDFP.td:13
+
+// We provide no sceduling info for the DFP instructions.
+// While they are not pseudo instructions we don't intend on scheduling them.
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Typo.


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Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.td:371
+// completely correct. However, since we are not pattern matching any
+// instrctions for these registers and we are not register allocating or
+// scheduling any of these instructions it should be safe to do this.
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Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.td:374
+// The reason we didn't use the correct type (Decimal Floating Point) is that
+// at the time of this implementation the correct type is not available.
+def FpRC :
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I think this is meant to be speaking in past tense, right?


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Comment at: llvm/test/MC/PowerPC/ppc64-encoding-dfp.s:1
+
+# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
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Nit: extra line.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D148597/new/

https://reviews.llvm.org/D148597