[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads

[Luke Lau via Phabricator via llvm-commits]

luke marked 3 inline comments as done.
luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11441
+    else if (BaseLdVT.isFloatingPoint())
+      WideScalarVT = MVT::getFloatingPointVT(WideScalarBitWidth);
+    else
----------------
craig.topper wrote:
> craig.topper wrote:
> > luke wrote:
> > > craig.topper wrote:
> > > > Wondering if we should always do integer in case f64 vector isn't supported, but i64 is?
> > > Good point, I couldn't recreate a test case for this though because we always check that `VT` is legal first. I also tried removing the legal type check, but then we get an assertion when calling `convertFromScalableVector` with an illegal type.
> > The case I was thinking was something like a concat of 2 v2f32 vectors which we would widen to a v2f64 strided load?
> On a Zve64f target that doesn't support Zve64d.
Ah that makes sense. Added a RUN line for it, should be covered by `@strided_runtime_4xv2f32`


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D147713/new/

https://reviews.llvm.org/D147713