[PATCH] D148347: [AArch64] Handle vector with two different values

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added a comment.

um... It seems the vector_shuffle's output is better than vselect's one as below even though it generates the constant pool. The vector_shuffle is lowered to tbl. Let me try to use vector_shuffle.
Additionally, AArch64 target expands the vselect so we need to expand it manually or add tablegen patterns for it...

  SelectionDAG has 16 nodes:
    t0: ch,glue = EntryToken
            t2: i64,ch = CopyFromReg t0, Register:i64 %0
          t23: i32,ch = load<(load (s8) from %ir.a), anyext from i8> t0, t2, undef:i64
        t26: v16i8 = AArch64ISD::DUP t23
            t41: i64 = AArch64ISD::ADRP TargetConstantPool:i64<<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, 
  i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>> 0 [TF=1]
          t42: i64 = AArch64ISD::ADDlow t41, TargetConstantPool:i64<<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i
  8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>> 0 [TF=34]
        t38: v16i8,ch = load<(load (s128) from constant-pool)> t0, t42, undef:i64
      t36: v16i8 = llvm.aarch64.neon.tbl1 Constant:i32<609>, t26, t38  --> tbl is generated.
    t16: ch,glue = CopyToReg t0, Register:v16i8 $q0, t36
    t17: ch = AArch64ISD::RET_GLUE t16, Register:v16i8 $q0, t16:1
  
  Assembly output
  test3:                                  // @test3
          .cfi_startproc
  // %bb.0:                               // %entry
          adrp    x8, .LCPI0_0
          ld1r    { v0.16b }, [x0]
          ldr     q1, [x8, :lo12:.LCPI0_0]
          tbl     v0.16b, { v0.16b }, v1.16b
          ret


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  https://reviews.llvm.org/D148347/new/

https://reviews.llvm.org/D148347