[PATCH] D148438: [AMDGPU] Do not crash on unknown register in AMDGPUResourceUsageAnalysis

[Pierre van Houtryve via Phabricator via llvm-commits]

Pierre-vh updated this revision to Diff 514537.
Pierre-vh marked 3 inline comments as done.
Pierre-vh added a comment.

Add the assert back in


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148438/new/

https://reviews.llvm.org/D148438

Files:
  llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
  llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir


Index: llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
@@ -0,0 +1,22 @@
+# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=amdgpu-resource-usage -verify-machineinstrs %s -o -
+
+# Checks that ResourceUsageAnalysis does not assert if it sees agpr_lo16, agpr_hi16 or TTMP regs.
+---
+
+name: test
+tracksRegLiveness: true
+frameInfo:
+  hasCalls: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $ttmp0, $ttmp0_ttmp1, $ttmp0_ttmp1_ttmp2_ttmp3
+    $vgpr0 = COPY $ttmp0
+    $vgpr1_vgpr2 = COPY $ttmp0_ttmp1
+    $vgpr1_vgpr2_vgpr3_vgpr4 = COPY $ttmp0_ttmp1_ttmp2_ttmp3
+    $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 = COPY $ttmp0_ttmp1_ttmp2_ttmp3_ttmp4_ttmp5_ttmp6_ttmp7
+    $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16 = COPY $ttmp0_ttmp1_ttmp2_ttmp3_ttmp4_ttmp5_ttmp6_ttmp7_ttmp8_ttmp9_ttmp10_ttmp11_ttmp12_ttmp13_ttmp14_ttmp15
+    $agpr1_lo16 = IMPLICIT_DEF
+    $agpr1_hi16 = IMPLICIT_DEF
+    $sgpr2_sgpr3 = SI_CALL undef $sgpr0_sgpr1, 0, CustomRegMask()
+    S_ENDPGM 0
+...
Index: llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp
@@ -484,11 +484,14 @@
           IsAGPR = true;
           Width = 32;
         } else {
+          // We only expect TTMP registers or registers that do not belong to
+          // any RC.
           assert((AMDGPU::TTMP_32RegClass.contains(Reg) ||
                   AMDGPU::TTMP_64RegClass.contains(Reg) ||
                   AMDGPU::TTMP_128RegClass.contains(Reg) ||
                   AMDGPU::TTMP_256RegClass.contains(Reg) ||
-                  AMDGPU::TTMP_512RegClass.contains(Reg)) &&
+                  AMDGPU::TTMP_512RegClass.contains(Reg) ||
+                  !TRI.getPhysRegBaseClass(Reg)) &&
                  "Unknown register class");
         }
         unsigned HWReg = TRI.getHWRegIndex(Reg);


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