[PATCH] D148519: [RISCV] Support vector strict rounding operations.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2572
+
+  // To catch overflow exception, use target strict operations when converting
+  // to integer.
----------------
fakepaper56 wrote:
> craig.topper wrote:
> > craig.topper wrote:
> > > There shouldn't be an overflow exception. If the value is already an "integer" in the FP register we shouldn't go through the integer conversion. The integer conversion only exists because of an oddity of the RISC-V ISA. That's not part of the definition of these functions.
> > > 
> > > The one thing we need to do that the non-strict doesn't handle is converting snan to qnan.
> > And we need to avoid raising an inexact exception for nearbyint.
> > The one thing we need to do that the non-strict doesn't handle is converting snan to qnan.
> Sorry, I don't know why we need to covert snan to qnan? Could you elaborate it ?
A signaling nan input should set the invalid exception and produce a quiet nan output. I believe the the glibc library implementation handles it by adding the input to itself if the input is nan. The fadd instruction produces qnan for an snan input and raises the invalid exception.


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https://reviews.llvm.org/D148519