[PATCH] D148519: [RISCV] Support vector strict rounding operations.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2572
+
+  // To catch overflow exception, use target strict operations when converting
+  // to integer.
----------------
There shouldn't be an overflow exception. If the value is already an "integer" in the FP register we shouldn't go through the integer conversion. The integer conversion only exists because of an oddity of the RISC-V ISA. That's not part of the definition of these functions.

The one thing we need to do that the non-strict doesn't handle is converting snan to qnan.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148519/new/

https://reviews.llvm.org/D148519