[llvm] beefca7 - [InstCombine][NFC] Add tests for simplifying select(X|Y,X|Y,X) to X|Y
Congcong Cai via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 17 13:07:21 PDT 2023
Author: Congcong Cai
Date: 2023-04-17T22:06:45+02:00
New Revision: beefca7239fc72967e5844540f6c820a54df9833
URL: https://github.com/llvm/llvm-project/commit/beefca7239fc72967e5844540f6c820a54df9833
DIFF: https://github.com/llvm/llvm-project/commit/beefca7239fc72967e5844540f6c820a54df9833.diff
LOG: [InstCombine][NFC] Add tests for simplifying select(X|Y,X|Y,X) to X|Y
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D148562
Added:
llvm/test/Transforms/InstSimplify/select_or_and.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstSimplify/select_or_and.ll b/llvm/test/Transforms/InstSimplify/select_or_and.ll
new file mode 100644
index 0000000000000..599b783cfac2a
--- /dev/null
+++ b/llvm/test/Transforms/InstSimplify/select_or_and.ll
@@ -0,0 +1,211 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=instsimplify < %s | FileCheck %s
+
+; select(Y | X == 0, X, Y | X)
+define i32 @select_or_1(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_or_1(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], 0
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %or = or i32 %y, %x
+ %cmp = icmp eq i32 %or, 0
+ %ret = select i1 %cmp, i32 %x, i32 %or
+ ret i32 %ret
+}
+
+; select(Y | X == 0, Y, Y | X)
+define i32 @select_or_2(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_or_2(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], 0
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %or = or i32 %y, %x
+ %cmp = icmp eq i32 %or, 0
+ %ret = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %ret
+}
+
+; select(Y | X != 0, Y | X, X)
+define i32 @select_or_3(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_or_3(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[OR]], 0
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[X]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %or = or i32 %y, %x
+ %cmp = icmp ne i32 %or, 0
+ %ret = select i1 %cmp, i32 %or, i32 %x
+ ret i32 %ret
+}
+
+; select(Y | X != 0, Y | X, Y)
+define i32 @select_or_4(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_or_4(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[OR]], 0
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %or = or i32 %y, %x
+ %cmp = icmp ne i32 %or, 0
+ %ret = select i1 %cmp, i32 %or, i32 %y
+ ret i32 %ret
+}
+
+; select(Y | X != 0, Y | X, Y)
+define <4 x i32> @select_or_vec(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @select_or_vec(
+; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne <4 x i32> [[OR]], zeroinitializer
+; CHECK-NEXT: [[RET:%.*]] = select <4 x i1> [[CMP]], <4 x i32> [[OR]], <4 x i32> [[Y]]
+; CHECK-NEXT: ret <4 x i32> [[RET]]
+;
+ %or = or <4 x i32> %y, %x
+ %cmp = icmp ne <4 x i32> %or, zeroinitializer
+ %ret = select <4 x i1> %cmp, <4 x i32> %or, <4 x i32> %y
+ ret <4 x i32> %ret
+}
+
+; select(Y | X == 0, Y | X, Y)
+define i32 @select_or_not_1(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_or_not_1(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], 0
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[OR]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %or = or i32 %y, %x
+ %cmp = icmp eq i32 %or, 0
+ %ret = select i1 %cmp, i32 %or, i32 %y
+ ret i32 %ret
+}
+; select(Y | X != 0, Y, Y | X)
+define i32 @select_or_not_2(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_or_not_2(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[OR]], 0
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %or = or i32 %y, %x
+ %cmp = icmp ne i32 %or, 0
+ %ret = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %ret
+}
+; select(Y | X != 1, Y, Y | X)
+define i32 @select_or_not_3(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_or_not_3(
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[OR]], 1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %or = or i32 %y, %x
+ %cmp = icmp ne i32 %or, 1
+ %ret = select i1 %cmp, i32 %y, i32 %or
+ ret i32 %ret
+}
+
+; select(Y & X == -1, X, Y & X)
+define i32 @select_and_1(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_and_1(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], -1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[AND]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %and = and i32 %y, %x
+ %cmp = icmp eq i32 %and, -1
+ %ret = select i1 %cmp, i32 %x, i32 %and
+ ret i32 %ret
+}
+
+; select(Y & X == -1, Y, Y & X)
+define i32 @select_and_2(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_and_2(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], -1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %and = and i32 %y, %x
+ %cmp = icmp eq i32 %and, -1
+ %ret = select i1 %cmp, i32 %y, i32 %and
+ ret i32 %ret
+}
+
+
+; select(Y & X != -1, Y & X, X)
+define i32 @select_and_3(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_and_3(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], -1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[AND]], i32 [[X]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %and = and i32 %y, %x
+ %cmp = icmp ne i32 %and, -1
+ %ret = select i1 %cmp, i32 %and, i32 %x
+ ret i32 %ret
+}
+
+; select(Y & X != -1, Y & X, Y)
+define i32 @select_and_4(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_and_4(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], -1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[AND]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %and = and i32 %y, %x
+ %cmp = icmp ne i32 %and, -1
+ %ret = select i1 %cmp, i32 %and, i32 %y
+ ret i32 %ret
+}
+
+; select(Y & X != -1, Y, Y & X)
+define i32 @select_and_not_1(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_and_not_1(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], -1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[AND]], i32 [[Y]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %and = and i32 %y, %x
+ %cmp = icmp eq i32 %and, -1
+ %ret = select i1 %cmp, i32 %and, i32 %y
+ ret i32 %ret
+}
+
+; select(Y & X != -1, Y, Y & X)
+define i32 @select_and_not_2(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_and_not_2(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], -1
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %and = and i32 %y, %x
+ %cmp = icmp ne i32 %and, -1
+ %ret = select i1 %cmp, i32 %y, i32 %and
+ ret i32 %ret
+}
+
+; select(Y & X != 123, Y, Y & X)
+define i32 @select_and_not_3(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_and_not_3(
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 123
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %and = and i32 %y, %x
+ %cmp = icmp ne i32 %and, 123
+ %ret = select i1 %cmp, i32 %y, i32 %and
+ ret i32 %ret
+}
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