[PATCH] D148317: [RISCV] Remove SEW=8 case for floating point

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:37
+                        !eq(mx, "MF4"): [16],
+                        !eq(mx, "MF8"): []);
+}
----------------
pcwang-thead wrote:
> pcwang-thead wrote:
> > michaelmaitland wrote:
> > > Under the vector specification, what does it mean for a vector floating point instruction to execute under MF8? Is this allowed?
> > > 
> > > In our scheduler, what does it mean for a vector floating point pseudo to be MF8? Under this implementation, does it mean we do not define scheduling resources for it since sew set is empty?
> > > 
> > > I wonder whether we need a `MxListF` that does not contain MF8, if it is the case that floating point vector instructions under MF8 don't make sense.
> > > Under the vector specification, what does it mean for a vector floating point instruction to execute under MF8? Is this allowed?
> > My understanding is:
> > 1. `SEW=8` is illegal since there is no standard 8 bits floating point format currently.
> > 2. The spec (3.4.2. Vector Register Grouping) says:
> > ```
> > In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value.
> > When LMUL < SEWMIN/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice. For example, with VLEN=ELEN=32, and SEW MIN=8, an LMUL of 1/8 would only provide four bits of storage in a vector register.
> > ```
> > 3. `MF8` may be legal, but it depends on `VLEN`. So, as you can see, there is no mf8 types in C API([Data Types](https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#data-types)) and LLVM IR ([Vector type mapping to LLVM types](https://github.com/llvm/llvm-project/blob/9fdf82dc32dc38e0b92dab3215a83d8f3c2f9bbf/llvm/lib/Target/RISCV/RISCVRegisterInfo.td#L267)).
> > 
> > > In our scheduler, what does it mean for a vector floating point pseudo to be MF8? Under this implementation, does it mean we do not define scheduling resources for it since sew set is empty?
> > 
> > Yes, we won't define any scheduling resources for it as we won't generate MF8 pseudos(see https://github.com/llvm/llvm-project/blob/9fdf82dc32dc38e0b92dab3215a83d8f3c2f9bbf/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td#L112).
> > 
> > > I wonder whether we need a MxListF that does not contain MF8, if it is the case that floating point vector instructions under MF8 don't make sense.
> > It makes sense to me to add a `MxListF`. I keep the MF8 case in `SchedSEWSetF` just because there is no `MxList` parameter in `LMULSEWWriteResImpl` and `LMULSEWReadAdvanceImpl`(we iterate over `SchedMxList`). A `!exist` can be added just like `LMULWriteResImpl` and `LMULReadAdvanceImpl`.
> Nope……
> We can't use `!exists` since we need to get `sews` first.
```
multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
                               bit isF = 0> {
  def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
  // Now I think we can remove MF8 from SchedSEWSetF
  foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
    defvar sews = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val); 
    foreach sew = sews in
      def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
  }
}
```


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https://reviews.llvm.org/D148317