[PATCH] D148523: [LegalizeTypes][VP] Widen fixed length vectors to VP nodes

[Luke Lau via Phabricator via llvm-commits]

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If we have a node with an illegal fixed length vector result type that
needs widened, e.g. `x:v6i32 = add a, b`
Instead of just widening it to: `x:v8i32 = add a, b`
We can widen it to the equivalent VP operation and set the EVL to the
exact number of elements needed: `x:v8i32 = vp_add a, b, mask=true, evl=6`
Provided that the target supports the equivalent VP operation on the
widened type.

This patch applies this technique when widening unary, binary and
ternary ops, as well as selects, loads and stores, but there are more
places this could be applied.

For loads and stores, scalable vectors are already widened using VP ops,
so there the existing logic is just reused for fixed length vectors.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148523

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  llvm/test/CodeGen/VE/Vector/vec_add.ll
  llvm/test/CodeGen/VE/Vector/vec_and.ll

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