[PATCH] D148510: [RISCV] Fix RUN line in fixed-vectors-abs-vp.ll

[Luke Lau via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGae1540b77c90: [RISCV] Fix RUN line in fixed-vectors-abs-vp.ll (authored by luke).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148510/new/

https://reviews.llvm.org/D148510

Files:
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll


Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
@@ -1,4 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK


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