[llvm] ae1540b - [RISCV] Fix RUN line in fixed-vectors-abs-vp.ll

[Luke Lau via llvm-commits]

Author: Luke Lau
Date: 2023-04-17T14:01:26+01:00
New Revision: ae1540b77c902580e547c849adfa3ba0e9530ad8

URL: https://github.com/llvm/llvm-project/commit/ae1540b77c902580e547c849adfa3ba0e9530ad8
DIFF: https://github.com/llvm/llvm-project/commit/ae1540b77c902580e547c849adfa3ba0e9530ad8.diff

LOG: [RISCV] Fix RUN line in fixed-vectors-abs-vp.ll

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D148510

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
index 497c580b99bfc..0b58eb6ad726e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
@@ -1,4 +1,5 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK