[llvm] f555fd5 - [LV] Regenreate check lines fr pr33706.ll

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2023-04-17T13:49:49+01:00
New Revision: f555fd5d8386d2d4f61a2675142af6b41a2f2972

URL: https://github.com/llvm/llvm-project/commit/f555fd5d8386d2d4f61a2675142af6b41a2f2972
DIFF: https://github.com/llvm/llvm-project/commit/f555fd5d8386d2d4f61a2675142af6b41a2f2972.diff

LOG: [LV] Regenreate check lines fr pr33706.ll

This avoids conflicts when regenerating check lines.

Added: 
    

Modified: 
    llvm/test/Transforms/LoopVectorize/pr33706.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopVectorize/pr33706.ll b/llvm/test/Transforms/LoopVectorize/pr33706.ll
index 20d58f4cf47f..e37f69cbd214 100644
--- a/llvm/test/Transforms/LoopVectorize/pr33706.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr33706.ll
@@ -1,12 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --prefix-filecheck-ir-name VAR_ --version 2
 ; RUN: opt -S -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=2 < %s | FileCheck %s
 
 @global = local_unnamed_addr global i32 0, align 4
 @global.1 = local_unnamed_addr global i32 0, align 4
 @global.2 = local_unnamed_addr global float 0x3EF0000000000000, align 4
 
-; CHECK-LABEL: @PR33706
-; CHECK-NOT: <2 x i32>
 define void @PR33706(ptr nocapture readonly %arg, ptr nocapture %arg1, i32 %arg2) local_unnamed_addr {
+; CHECK-LABEL: define void @PR33706
+; CHECK-SAME: (ptr nocapture readonly [[ARG:%.*]], ptr nocapture [[ARG1:%.*]], i32 [[ARG2:%.*]]) local_unnamed_addr {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = load i32, ptr @global.1, align 4
+; CHECK-NEXT:    [[VAR_TMP3:%.*]] = getelementptr inbounds float, ptr [[ARG]], i64 190
+; CHECK-NEXT:    [[VAR_TMP4:%.*]] = getelementptr inbounds float, ptr [[ARG1]], i64 512
+; CHECK-NEXT:    [[VAR_TMP5:%.*]] = and i32 [[TMP]], 65535
+; CHECK-NEXT:    [[VAR_TMP6:%.*]] = icmp ugt i32 [[ARG2]], 65536
+; CHECK-NEXT:    br i1 [[VAR_TMP6]], label [[BB7:%.*]], label [[BB9:%.*]]
+; CHECK:       bb7:
+; CHECK-NEXT:    [[VAR_TMP8:%.*]] = load i32, ptr @global, align 4
+; CHECK-NEXT:    br label [[BB27:%.*]]
+; CHECK:       bb9:
+; CHECK-NEXT:    [[VAR_TMP10:%.*]] = udiv i32 65536, [[ARG2]]
+; CHECK-NEXT:    br label [[BB11:%.*]]
+; CHECK:       bb11:
+; CHECK-NEXT:    [[VAR_TMP12:%.*]] = phi i32 [ [[VAR_TMP20:%.*]], [[BB11]] ], [ [[VAR_TMP5]], [[BB9]] ]
+; CHECK-NEXT:    [[VAR_TMP13:%.*]] = phi ptr [ [[VAR_TMP18:%.*]], [[BB11]] ], [ [[VAR_TMP4]], [[BB9]] ]
+; CHECK-NEXT:    [[VAR_TMP14:%.*]] = phi i32 [ [[VAR_TMP16:%.*]], [[BB11]] ], [ [[VAR_TMP10]], [[BB9]] ]
+; CHECK-NEXT:    [[VAR_TMP15:%.*]] = phi i32 [ [[VAR_TMP19:%.*]], [[BB11]] ], [ [[TMP]], [[BB9]] ]
+; CHECK-NEXT:    [[VAR_TMP16]] = add nsw i32 [[VAR_TMP14]], -1
+; CHECK-NEXT:    [[VAR_TMP17:%.*]] = sitofp i32 [[VAR_TMP12]] to float
+; CHECK-NEXT:    store float [[VAR_TMP17]], ptr [[VAR_TMP13]], align 4
+; CHECK-NEXT:    [[VAR_TMP18]] = getelementptr inbounds float, ptr [[VAR_TMP13]], i64 1
+; CHECK-NEXT:    [[VAR_TMP19]] = add i32 [[VAR_TMP15]], [[ARG2]]
+; CHECK-NEXT:    [[VAR_TMP20]] = and i32 [[VAR_TMP19]], 65535
+; CHECK-NEXT:    [[VAR_TMP21:%.*]] = icmp eq i32 [[VAR_TMP16]], 0
+; CHECK-NEXT:    br i1 [[VAR_TMP21]], label [[BB22:%.*]], label [[BB11]]
+; CHECK:       bb22:
+; CHECK-NEXT:    [[VAR_TMP23:%.*]] = phi ptr [ [[VAR_TMP18]], [[BB11]] ]
+; CHECK-NEXT:    [[VAR_TMP24:%.*]] = phi i32 [ [[VAR_TMP19]], [[BB11]] ]
+; CHECK-NEXT:    [[VAR_TMP25:%.*]] = phi i32 [ [[VAR_TMP20]], [[BB11]] ]
+; CHECK-NEXT:    [[VAR_TMP26:%.*]] = ashr i32 [[VAR_TMP24]], 16
+; CHECK-NEXT:    store i32 [[VAR_TMP26]], ptr @global, align 4
+; CHECK-NEXT:    br label [[BB27]]
+; CHECK:       bb27:
+; CHECK-NEXT:    [[VAR_TMP28:%.*]] = phi i32 [ [[VAR_TMP26]], [[BB22]] ], [ [[VAR_TMP8]], [[BB7]] ]
+; CHECK-NEXT:    [[VAR_TMP29:%.*]] = phi ptr [ [[VAR_TMP23]], [[BB22]] ], [ [[VAR_TMP4]], [[BB7]] ]
+; CHECK-NEXT:    [[VAR_TMP30:%.*]] = phi i32 [ [[VAR_TMP25]], [[BB22]] ], [ [[VAR_TMP5]], [[BB7]] ]
+; CHECK-NEXT:    [[VAR_TMP31:%.*]] = sext i32 [[VAR_TMP28]] to i64
+; CHECK-NEXT:    [[VAR_TMP32:%.*]] = getelementptr inbounds float, ptr [[VAR_TMP3]], i64 [[VAR_TMP31]]
+; CHECK-NEXT:    [[VAR_TMP33:%.*]] = load float, ptr [[VAR_TMP32]], align 4
+; CHECK-NEXT:    [[VAR_TMP34:%.*]] = sitofp i32 [[VAR_TMP30]] to float
+; CHECK-NEXT:    [[VAR_TMP35:%.*]] = load float, ptr @global.2, align 4
+; CHECK-NEXT:    [[VAR_TMP36:%.*]] = fmul float [[VAR_TMP35]], [[VAR_TMP34]]
+; CHECK-NEXT:    [[VAR_TMP37:%.*]] = fadd float [[VAR_TMP33]], [[VAR_TMP36]]
+; CHECK-NEXT:    store float [[VAR_TMP37]], ptr [[VAR_TMP29]], align 4
+; CHECK-NEXT:    ret void
+;
 bb:
   %tmp = load i32, ptr @global.1, align 4
   %tmp3 = getelementptr inbounds float, ptr %arg, i64 190