[llvm] 8bf7f86 - Fix uninitialized pointer members in CodeGen
via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 17 01:33:03 PDT 2023
Author: Akshay Khadse
Date: 2023-04-17T16:32:46+08:00
New Revision: 8bf7f86d7966ff835967669fb6bf23897e20b71d
URL: https://github.com/llvm/llvm-project/commit/8bf7f86d7966ff835967669fb6bf23897e20b71d
DIFF: https://github.com/llvm/llvm-project/commit/8bf7f86d7966ff835967669fb6bf23897e20b71d.diff
LOG: Fix uninitialized pointer members in CodeGen
This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D148303
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/include/llvm/CodeGen/DebugHandlerBase.h
llvm/include/llvm/CodeGen/EdgeBundles.h
llvm/include/llvm/CodeGen/ExecutionDomainFix.h
llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
llvm/include/llvm/CodeGen/GlobalISel/Localizer.h
llvm/include/llvm/CodeGen/LatencyPriorityQueue.h
llvm/include/llvm/CodeGen/LiveIntervals.h
llvm/include/llvm/CodeGen/LiveRegMatrix.h
llvm/include/llvm/CodeGen/LiveStacks.h
llvm/include/llvm/CodeGen/LiveVariables.h
llvm/include/llvm/CodeGen/MIRFSDiscriminator.h
llvm/include/llvm/CodeGen/MachineModuleInfo.h
llvm/include/llvm/CodeGen/MachinePipeliner.h
llvm/include/llvm/CodeGen/MachineSSAUpdater.h
llvm/include/llvm/CodeGen/ModuloSchedule.h
llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
llvm/include/llvm/CodeGen/RegisterScavenging.h
llvm/include/llvm/CodeGen/RegisterUsageInfo.h
llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
llvm/include/llvm/CodeGen/StackProtector.h
llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h
llvm/lib/CodeGen/BranchFolding.h
llvm/lib/CodeGen/BranchRelaxation.cpp
llvm/lib/CodeGen/BreakFalseDeps.cpp
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
llvm/lib/CodeGen/DetectDeadLanes.cpp
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/ExpandMemCmp.cpp
llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
llvm/lib/CodeGen/GCRootLowering.cpp
llvm/lib/CodeGen/IfConversion.cpp
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/InterferenceCache.h
llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
llvm/lib/CodeGen/MachineBlockPlacement.cpp
llvm/lib/CodeGen/MachineCSE.cpp
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/OptimizePHIs.cpp
llvm/lib/CodeGen/PHIElimination.cpp
llvm/lib/CodeGen/PeepholeOptimizer.cpp
llvm/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/lib/CodeGen/PrologEpilogInserter.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocGreedy.h
llvm/lib/CodeGen/SelectOptimize.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
llvm/lib/CodeGen/ShrinkWrap.cpp
llvm/lib/CodeGen/SjLjEHPrepare.cpp
llvm/lib/CodeGen/SpillPlacement.h
llvm/lib/CodeGen/StackColoring.cpp
llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
llvm/lib/CodeGen/StackSlotColoring.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/CodeGen/VirtRegMap.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 15f76d8de2174..b6b4c18ad17f7 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -87,7 +87,7 @@ class AsmPrinter : public MachineFunctionPass {
TargetMachine &TM;
/// Target Asm Printer information.
- const MCAsmInfo *MAI;
+ const MCAsmInfo *MAI = nullptr;
/// This is the context for the output file that we are streaming. This owns
/// all of the global MC-related objects for the generated translation unit.
@@ -111,7 +111,7 @@ class AsmPrinter : public MachineFunctionPass {
MachineLoopInfo *MLI = nullptr;
/// Optimization remark emitter.
- MachineOptimizationRemarkEmitter *ORE;
+ MachineOptimizationRemarkEmitter *ORE = nullptr;
/// The symbol for the entry in __patchable_function_entires.
MCSymbol *CurrentPatchableFunctionEntrySym = nullptr;
diff --git a/llvm/include/llvm/CodeGen/DebugHandlerBase.h b/llvm/include/llvm/CodeGen/DebugHandlerBase.h
index 1b7355f5d9fbb..af25f2544da71 100644
--- a/llvm/include/llvm/CodeGen/DebugHandlerBase.h
+++ b/llvm/include/llvm/CodeGen/DebugHandlerBase.h
@@ -55,10 +55,10 @@ class DebugHandlerBase : public AsmPrinterHandler {
DebugHandlerBase(AsmPrinter *A);
/// Target of debug info emission.
- AsmPrinter *Asm;
+ AsmPrinter *Asm = nullptr;
/// Collected machine module information.
- MachineModuleInfo *MMI;
+ MachineModuleInfo *MMI = nullptr;
/// Previous instruction's location information. This is used to
/// determine label location to indicate scope boundaries in debug info.
@@ -73,7 +73,7 @@ class DebugHandlerBase : public AsmPrinterHandler {
DebugLoc PrologEndLoc;
/// This block includes epilogue instructions.
- const MachineBasicBlock *EpilogBeginBlock;
+ const MachineBasicBlock *EpilogBeginBlock = nullptr;
/// If nonnull, stores the current machine instruction we're processing.
const MachineInstr *CurMI = nullptr;
diff --git a/llvm/include/llvm/CodeGen/EdgeBundles.h b/llvm/include/llvm/CodeGen/EdgeBundles.h
index b6187fc6dcef5..b844bd307c197 100644
--- a/llvm/include/llvm/CodeGen/EdgeBundles.h
+++ b/llvm/include/llvm/CodeGen/EdgeBundles.h
@@ -22,7 +22,7 @@
namespace llvm {
class EdgeBundles : public MachineFunctionPass {
- const MachineFunction *MF;
+ const MachineFunction *MF = nullptr;
/// EC - Each edge bundle is an equivalence class. The keys are:
/// 2*BB->getNumber() -> Ingoing bundle.
diff --git a/llvm/include/llvm/CodeGen/ExecutionDomainFix.h b/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
index d052905791d74..4e2b171c73cc0 100644
--- a/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
+++ b/llvm/include/llvm/CodeGen/ExecutionDomainFix.h
@@ -118,9 +118,9 @@ class ExecutionDomainFix : public MachineFunctionPass {
SmallVector<DomainValue *, 16> Avail;
const TargetRegisterClass *const RC;
- MachineFunction *MF;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
+ MachineFunction *MF = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
std::vector<SmallVector<int, 1>> AliasMap;
const unsigned NumRegs;
/// Value currently in each register, or NULL when no value is being tracked.
@@ -133,7 +133,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
using OutRegsInfoMap = SmallVector<LiveRegsDVInfo, 4>;
OutRegsInfoMap MBBOutRegsInfos;
- ReachingDefAnalysis *RDA;
+ ReachingDefAnalysis *RDA = nullptr;
public:
ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 48c49c22f81d0..b0d2fed49bc74 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -67,7 +67,7 @@ class IRTranslator : public MachineFunctionPass {
private:
/// Interface used to lower the everything related to calls.
- const CallLowering *CLI;
+ const CallLowering *CLI = nullptr;
/// This class contains the mapping between the Values to vreg related data.
class ValueToVRegInfo {
@@ -553,24 +553,24 @@ class IRTranslator : public MachineFunctionPass {
std::unique_ptr<MachineIRBuilder> EntryBuilder;
// The MachineFunction currently being translated.
- MachineFunction *MF;
+ MachineFunction *MF = nullptr;
/// MachineRegisterInfo used to create virtual registers.
MachineRegisterInfo *MRI = nullptr;
- const DataLayout *DL;
+ const DataLayout *DL = nullptr;
/// Current target configuration. Controls how the pass handles errors.
- const TargetPassConfig *TPC;
+ const TargetPassConfig *TPC = nullptr;
CodeGenOpt::Level OptLevel;
/// Current optimization remark emitter. Used to report failures.
std::unique_ptr<OptimizationRemarkEmitter> ORE;
- AAResults *AA;
- AssumptionCache *AC;
- const TargetLibraryInfo *LibInfo;
+ AAResults *AA = nullptr;
+ AssumptionCache *AC = nullptr;
+ const TargetLibraryInfo *LibInfo = nullptr;
FunctionLoweringInfo FuncInfo;
// True when either the Target Machine specifies no optimizations or the
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h b/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
index 466dbed537e29..eb66896ed2be1 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LoadStoreOpt.h
@@ -69,11 +69,11 @@ class LoadStoreOpt : public MachineFunctionPass {
/// on the given MachineFunction.
std::function<bool(const MachineFunction &)> DoNotRunPass;
- MachineRegisterInfo *MRI;
- const TargetLowering *TLI;
- MachineFunction *MF;
- AliasAnalysis *AA;
- const LegalizerInfo *LI;
+ MachineRegisterInfo *MRI = nullptr;
+ const TargetLowering *TLI = nullptr;
+ MachineFunction *MF = nullptr;
+ AliasAnalysis *AA = nullptr;
+ const LegalizerInfo *LI = nullptr;
MachineIRBuilder Builder;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h b/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h
index 9ea0d095eeb11..b1fcdd207a60a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Localizer.h
@@ -51,9 +51,9 @@ class Localizer : public MachineFunctionPass {
/// MRI contains all the register class/bank information that this
/// pass uses and updates.
- MachineRegisterInfo *MRI;
+ MachineRegisterInfo *MRI = nullptr;
/// TTI used for getting remat costs for instructions.
- TargetTransformInfo *TTI;
+ TargetTransformInfo *TTI = nullptr;
/// Check if \p MOUse is used in the same basic block as \p Def.
/// If the use is in the same block, we say it is local.
diff --git a/llvm/include/llvm/CodeGen/LatencyPriorityQueue.h b/llvm/include/llvm/CodeGen/LatencyPriorityQueue.h
index 95f4c6473542e..556ef3f8cc788 100644
--- a/llvm/include/llvm/CodeGen/LatencyPriorityQueue.h
+++ b/llvm/include/llvm/CodeGen/LatencyPriorityQueue.h
@@ -31,7 +31,7 @@ namespace llvm {
class LatencyPriorityQueue : public SchedulingPriorityQueue {
// SUnits - The SUnits for the current graph.
- std::vector<SUnit> *SUnits;
+ std::vector<SUnit> *SUnits = nullptr;
/// NumNodesSolelyBlocking - This vector contains, for every node in the
/// Queue, the number of nodes that the node is the sole unscheduled
diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h
index 0c846c6671a74..f972dd0136c73 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervals.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervals.h
@@ -51,11 +51,11 @@ class TargetInstrInfo;
class VirtRegMap;
class LiveIntervals : public MachineFunctionPass {
- MachineFunction* MF;
- MachineRegisterInfo* MRI;
- const TargetRegisterInfo* TRI;
- const TargetInstrInfo *TII;
- SlotIndexes* Indexes;
+ MachineFunction *MF = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ SlotIndexes *Indexes = nullptr;
MachineDominatorTree *DomTree = nullptr;
LiveIntervalCalc *LICalc = nullptr;
diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
index 9e28e4d243c29..2b32308c7c075 100644
--- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h
+++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h
@@ -38,9 +38,9 @@ class TargetRegisterInfo;
class VirtRegMap;
class LiveRegMatrix : public MachineFunctionPass {
- const TargetRegisterInfo *TRI;
- LiveIntervals *LIS;
- VirtRegMap *VRM;
+ const TargetRegisterInfo *TRI = nullptr;
+ LiveIntervals *LIS = nullptr;
+ VirtRegMap *VRM = nullptr;
// UserTag changes whenever virtual registers have been modified.
unsigned UserTag = 0;
diff --git a/llvm/include/llvm/CodeGen/LiveStacks.h b/llvm/include/llvm/CodeGen/LiveStacks.h
index 26f30fb4d088b..2edc2985f0ee6 100644
--- a/llvm/include/llvm/CodeGen/LiveStacks.h
+++ b/llvm/include/llvm/CodeGen/LiveStacks.h
@@ -33,7 +33,7 @@ class TargetRegisterClass;
class TargetRegisterInfo;
class LiveStacks : public MachineFunctionPass {
- const TargetRegisterInfo *TRI;
+ const TargetRegisterInfo *TRI = nullptr;
/// Special pool allocator for VNInfo's (LiveInterval val#).
///
diff --git a/llvm/include/llvm/CodeGen/LiveVariables.h b/llvm/include/llvm/CodeGen/LiveVariables.h
index 03a0517d2642d..a1ed3c073251b 100644
--- a/llvm/include/llvm/CodeGen/LiveVariables.h
+++ b/llvm/include/llvm/CodeGen/LiveVariables.h
@@ -124,11 +124,11 @@ class LiveVariables : public MachineFunctionPass {
SparseBitVector<> PHIJoins;
private: // Intermediate data structures
- MachineFunction *MF;
+ MachineFunction *MF = nullptr;
- MachineRegisterInfo* MRI;
+ MachineRegisterInfo *MRI = nullptr;
- const TargetRegisterInfo *TRI;
+ const TargetRegisterInfo *TRI = nullptr;
// PhysRegInfo - Keep track of which instruction was the last def of a
// physical register. This is a purely local property, because all physical
diff --git a/llvm/include/llvm/CodeGen/MIRFSDiscriminator.h b/llvm/include/llvm/CodeGen/MIRFSDiscriminator.h
index 3bbcfd63e3aa5..1ab55a7d4f0ca 100644
--- a/llvm/include/llvm/CodeGen/MIRFSDiscriminator.h
+++ b/llvm/include/llvm/CodeGen/MIRFSDiscriminator.h
@@ -30,7 +30,7 @@ class MachineFunction;
using namespace sampleprof;
class MIRAddFSDiscriminators : public MachineFunctionPass {
- MachineFunction *MF;
+ MachineFunction *MF = nullptr;
unsigned LowBit;
unsigned HighBit;
diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h
index ea07e365d465d..d774653c6ed18 100644
--- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h
+++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h
@@ -84,7 +84,7 @@ class MachineModuleInfo {
MCContext *ExternalContext = nullptr;
/// This is the LLVM Module being worked on.
- const Module *TheModule;
+ const Module *TheModule = nullptr;
/// This is the object-file-format-specific implementation of
/// MachineModuleInfoImpl, which lets targets accumulate whatever info they
diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h
index f8ae9a6c576b0..3833d80f503ab 100644
--- a/llvm/include/llvm/CodeGen/MachinePipeliner.h
+++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h
@@ -69,7 +69,7 @@ class MachinePipeliner : public MachineFunctionPass {
MachineOptimizationRemarkEmitter *ORE = nullptr;
const MachineLoopInfo *MLI = nullptr;
const MachineDominatorTree *MDT = nullptr;
- const InstrItineraryData *InstrItins;
+ const InstrItineraryData *InstrItins = nullptr;
const TargetInstrInfo *TII = nullptr;
RegisterClassInfo RegClassInfo;
bool disabledByPragma = false;
diff --git a/llvm/include/llvm/CodeGen/MachineSSAUpdater.h b/llvm/include/llvm/CodeGen/MachineSSAUpdater.h
index 3f0b55e0abb86..bbd09d7d151ba 100644
--- a/llvm/include/llvm/CodeGen/MachineSSAUpdater.h
+++ b/llvm/include/llvm/CodeGen/MachineSSAUpdater.h
@@ -41,14 +41,14 @@ class MachineSSAUpdater {
void *AV = nullptr;
/// VRC - Register class of the current virtual register.
- const TargetRegisterClass *VRC;
+ const TargetRegisterClass *VRC = nullptr;
/// InsertedPHIs - If this is non-null, the MachineSSAUpdater adds all PHI
/// nodes that it creates to the vector.
SmallVectorImpl<MachineInstr*> *InsertedPHIs;
- const TargetInstrInfo *TII;
- MachineRegisterInfo *MRI;
+ const TargetInstrInfo *TII = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
public:
/// MachineSSAUpdater constructor. If InsertedPHIs is specified, it will be
diff --git a/llvm/include/llvm/CodeGen/ModuloSchedule.h b/llvm/include/llvm/CodeGen/ModuloSchedule.h
index b9213ab58aa4b..d03f7b4959159 100644
--- a/llvm/include/llvm/CodeGen/ModuloSchedule.h
+++ b/llvm/include/llvm/CodeGen/ModuloSchedule.h
@@ -170,11 +170,11 @@ class ModuloScheduleExpander {
MachineFunction &MF;
const TargetSubtargetInfo &ST;
MachineRegisterInfo &MRI;
- const TargetInstrInfo *TII;
+ const TargetInstrInfo *TII = nullptr;
LiveIntervals &LIS;
- MachineBasicBlock *BB;
- MachineBasicBlock *Preheader;
+ MachineBasicBlock *BB = nullptr;
+ MachineBasicBlock *Preheader = nullptr;
MachineBasicBlock *NewKernel = nullptr;
std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> LoopInfo;
@@ -297,13 +297,13 @@ class PeelingModuloScheduleExpander {
MachineFunction &MF;
const TargetSubtargetInfo &ST;
MachineRegisterInfo &MRI;
- const TargetInstrInfo *TII;
- LiveIntervals *LIS;
+ const TargetInstrInfo *TII = nullptr;
+ LiveIntervals *LIS = nullptr;
/// The original loop block that gets rewritten in-place.
- MachineBasicBlock *BB;
+ MachineBasicBlock *BB = nullptr;
/// The original loop preheader.
- MachineBasicBlock *Preheader;
+ MachineBasicBlock *Preheader = nullptr;
/// All prolog and epilog blocks.
SmallVector<MachineBasicBlock *, 4> Prologs, Epilogs;
/// For every block, the stages that are produced.
diff --git a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
index 630f9dab2d1d8..60c6994c2a551 100644
--- a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
+++ b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
@@ -68,8 +68,8 @@ struct PointerLikeTypeTraits<ReachingDef> {
/// This class provides the reaching def analysis.
class ReachingDefAnalysis : public MachineFunctionPass {
private:
- MachineFunction *MF;
- const TargetRegisterInfo *TRI;
+ MachineFunction *MF = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
LoopTraversal::TraversalOrder TraversedMBBOrder;
unsigned NumRegUnits;
/// Instruction that defined each register, relative to the beginning of the
diff --git a/llvm/include/llvm/CodeGen/RegisterScavenging.h b/llvm/include/llvm/CodeGen/RegisterScavenging.h
index 52797afbd8486..e6995672931cf 100644
--- a/llvm/include/llvm/CodeGen/RegisterScavenging.h
+++ b/llvm/include/llvm/CodeGen/RegisterScavenging.h
@@ -32,9 +32,9 @@ class TargetRegisterClass;
class TargetRegisterInfo;
class RegScavenger {
- const TargetRegisterInfo *TRI;
- const TargetInstrInfo *TII;
- MachineRegisterInfo* MRI;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
MachineBasicBlock *MBB = nullptr;
MachineBasicBlock::iterator MBBI;
unsigned NumRegUnits = 0;
diff --git a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h
index 8b406a2750251..aa1f5ef8110b0 100644
--- a/llvm/include/llvm/CodeGen/RegisterUsageInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterUsageInfo.h
@@ -63,7 +63,7 @@ class PhysicalRegisterUsageInfo : public ImmutablePass {
/// and 1 means content of register will be preserved around function call.
DenseMap<const Function *, std::vector<uint32_t>> RegMasks;
- const LLVMTargetMachine *TM;
+ const LLVMTargetMachine *TM = nullptr;
};
} // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index dc8f02e28adf4..0c97e45709d1b 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -119,7 +119,7 @@ namespace llvm {
/// A ScheduleDAG for scheduling lists of MachineInstr.
class ScheduleDAGInstrs : public ScheduleDAG {
protected:
- const MachineLoopInfo *MLI;
+ const MachineLoopInfo *MLI = nullptr;
const MachineFrameInfo &MFI;
/// TargetSchedModel provides an interface to the machine model.
@@ -143,7 +143,7 @@ namespace llvm {
// ------------------------------------------------
/// The block in which to insert instructions
- MachineBasicBlock *BB;
+ MachineBasicBlock *BB = nullptr;
/// The beginning of the range to be scheduled.
MachineBasicBlock::iterator RegionBegin;
diff --git a/llvm/include/llvm/CodeGen/StackProtector.h b/llvm/include/llvm/CodeGen/StackProtector.h
index 6bbdae69666fe..1f425dbd36545 100644
--- a/llvm/include/llvm/CodeGen/StackProtector.h
+++ b/llvm/include/llvm/CodeGen/StackProtector.h
@@ -49,8 +49,8 @@ class StackProtector : public FunctionPass {
const TargetLoweringBase *TLI = nullptr;
Triple Trip;
- Function *F;
- Module *M;
+ Function *F = nullptr;
+ Module *M = nullptr;
std::optional<DomTreeUpdater> DTU;
diff --git a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
index 47bedd9befc88..189dfef590b0f 100644
--- a/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
+++ b/llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
@@ -237,11 +237,11 @@ uint64_t getJumpTableNumCases(const SmallVectorImpl<unsigned> &TotalCases,
unsigned First, unsigned Last);
struct SwitchWorkListItem {
- MachineBasicBlock *MBB;
+ MachineBasicBlock *MBB = nullptr;
CaseClusterIt FirstCluster;
CaseClusterIt LastCluster;
- const ConstantInt *GE;
- const ConstantInt *LT;
+ const ConstantInt *GE = nullptr;
+ const ConstantInt *LT = nullptr;
BranchProbability DefaultProb;
};
using SwitchWorkList = SmallVector<SwitchWorkListItem, 4>;
@@ -292,9 +292,9 @@ class SwitchLowering {
virtual ~SwitchLowering() = default;
private:
- const TargetLowering *TLI;
- const TargetMachine *TM;
- const DataLayout *DL;
+ const TargetLowering *TLI = nullptr;
+ const TargetMachine *TM = nullptr;
+ const DataLayout *DL = nullptr;
FunctionLoweringInfo &FuncInfo;
};
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 71d0cb51e6f06..85c5ed2c4a5fe 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -3318,7 +3318,7 @@ class TargetLoweringBase {
/// register class is the largest legal super-reg register class of the
/// register class of the specified type. e.g. On x86, i8, i16, and i32's
/// representative class would be GR32.
- const TargetRegisterClass *RepRegClassForVT[MVT::VALUETYPE_SIZE];
+ const TargetRegisterClass *RepRegClassForVT[MVT::VALUETYPE_SIZE] = {0};
/// This indicates the "cost" of the "representative" register class for each
/// ValueType. The cost is used by the scheduler to approximate register
diff --git a/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h b/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h
index 0515173b4a24b..a96bdd0349186 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DebugLocStream.h
@@ -49,7 +49,7 @@ class DebugLocStream {
SmallVector<Entry, 32> Entries;
SmallString<256> DWARFBytes;
std::vector<std::string> Comments;
- MCSymbol *Sym;
+ MCSymbol *Sym = nullptr;
/// Only verbose textual output needs comments. This will be set to
/// true for that case, and false otherwise.
diff --git a/llvm/lib/CodeGen/BranchFolding.h b/llvm/lib/CodeGen/BranchFolding.h
index d0b6ed5ebe053..b7d0a5fcf9e74 100644
--- a/llvm/lib/CodeGen/BranchFolding.h
+++ b/llvm/lib/CodeGen/BranchFolding.h
@@ -118,10 +118,10 @@ class TargetRegisterInfo;
bool EnableHoistCommonCode;
bool UpdateLiveIns;
unsigned MinCommonTailLength;
- const TargetInstrInfo *TII;
- const MachineRegisterInfo *MRI;
- const TargetRegisterInfo *TRI;
- MachineLoopInfo *MLI;
+ const TargetInstrInfo *TII = nullptr;
+ const MachineRegisterInfo *MRI = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineLoopInfo *MLI = nullptr;
LivePhysRegs LiveRegs;
private:
diff --git a/llvm/lib/CodeGen/BranchRelaxation.cpp b/llvm/lib/CodeGen/BranchRelaxation.cpp
index 45c09a12ce110..05494f1ddc67e 100644
--- a/llvm/lib/CodeGen/BranchRelaxation.cpp
+++ b/llvm/lib/CodeGen/BranchRelaxation.cpp
@@ -81,9 +81,9 @@ class BranchRelaxation : public MachineFunctionPass {
std::unique_ptr<RegScavenger> RS;
LivePhysRegs LiveRegs;
- MachineFunction *MF;
- const TargetRegisterInfo *TRI;
- const TargetInstrInfo *TII;
+ MachineFunction *MF = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
bool relaxBranchInstructions();
void scanFunction();
diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp
index 3102731736473..5b5d670cdff1f 100644
--- a/llvm/lib/CodeGen/BreakFalseDeps.cpp
+++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp
@@ -34,9 +34,9 @@ namespace llvm {
class BreakFalseDeps : public MachineFunctionPass {
private:
- MachineFunction *MF;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
+ MachineFunction *MF = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
RegisterClassInfo RegClassInfo;
/// List of undefined register reads in this block in forward order.
@@ -45,7 +45,7 @@ class BreakFalseDeps : public MachineFunctionPass {
/// Storage for register unit liveness.
LivePhysRegs LiveRegSet;
- ReachingDefAnalysis *RDA;
+ ReachingDefAnalysis *RDA = nullptr;
public:
static char ID; // Pass identification, replacement for typeid
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index bd00c9fac9295..62253e603cdef 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -298,16 +298,16 @@ class TypePromotionTransaction;
class CodeGenPrepare : public FunctionPass {
const TargetMachine *TM = nullptr;
- const TargetSubtargetInfo *SubtargetInfo;
+ const TargetSubtargetInfo *SubtargetInfo = nullptr;
const TargetLowering *TLI = nullptr;
- const TargetRegisterInfo *TRI;
+ const TargetRegisterInfo *TRI = nullptr;
const TargetTransformInfo *TTI = nullptr;
const BasicBlockSectionsProfileReader *BBSectionsProfileReader = nullptr;
- const TargetLibraryInfo *TLInfo;
- const LoopInfo *LI;
+ const TargetLibraryInfo *TLInfo = nullptr;
+ const LoopInfo *LI = nullptr;
std::unique_ptr<BlockFrequencyInfo> BFI;
std::unique_ptr<BranchProbabilityInfo> BPI;
- ProfileSummaryInfo *PSI;
+ ProfileSummaryInfo *PSI = nullptr;
/// As we scan instructions optimizing them, this is the next instruction
/// to optimize. Transforms that can invalidate this should update it.
diff --git a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
index 36fad9e6f9585..ff0c5d530747b 100644
--- a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
+++ b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp
@@ -197,8 +197,8 @@ class ComplexDeinterleavingGraph {
explicit ComplexDeinterleavingGraph(const TargetLowering *tl) : TL(tl) {}
private:
- const TargetLowering *TL;
- Instruction *RootValue;
+ const TargetLowering *TL = nullptr;
+ Instruction *RootValue = nullptr;
NodePtr RootNode;
SmallVector<NodePtr> CompositeNodes;
SmallPtrSet<Instruction *, 16> AllInstructions;
diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
index e36db43567c5d..5fc1897dd2224 100644
--- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
+++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@@ -31,8 +31,8 @@ namespace {
class DeadMachineInstructionElim : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
- const MachineRegisterInfo *MRI;
- const TargetInstrInfo *TII;
+ const MachineRegisterInfo *MRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
LiveRegUnits LivePhysRegs;
public:
diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp
index 9d3452c2e2977..86e9f3abe010d 100644
--- a/llvm/lib/CodeGen/DetectDeadLanes.cpp
+++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp
@@ -403,8 +403,8 @@ class DetectDeadLanes : public MachineFunctionPass {
bool isUndefInput(const DeadLaneDetector &DLD, const MachineOperand &MO,
bool *CrossCopy) const;
- const MachineRegisterInfo *MRI;
- const TargetRegisterInfo *TRI;
+ const MachineRegisterInfo *MRI = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
};
} // end anonymous namespace
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index 4226a97c06fd1..a0dfff7270595 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -760,14 +760,14 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks,
namespace {
class EarlyIfConverter : public MachineFunctionPass {
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
MCSchedModel SchedModel;
- MachineRegisterInfo *MRI;
- MachineDominatorTree *DomTree;
- MachineLoopInfo *Loops;
- MachineTraceMetrics *Traces;
- MachineTraceMetrics::Ensemble *MinInstr;
+ MachineRegisterInfo *MRI = nullptr;
+ MachineDominatorTree *DomTree = nullptr;
+ MachineLoopInfo *Loops = nullptr;
+ MachineTraceMetrics *Traces = nullptr;
+ MachineTraceMetrics::Ensemble *MinInstr = nullptr;
SSAIfConv IfConv;
public:
@@ -1084,13 +1084,13 @@ bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
namespace {
class EarlyIfPredicator : public MachineFunctionPass {
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
TargetSchedModel SchedModel;
- MachineRegisterInfo *MRI;
- MachineDominatorTree *DomTree;
- MachineBranchProbabilityInfo *MBPI;
- MachineLoopInfo *Loops;
+ MachineRegisterInfo *MRI = nullptr;
+ MachineDominatorTree *DomTree = nullptr;
+ MachineBranchProbabilityInfo *MBPI = nullptr;
+ MachineLoopInfo *Loops = nullptr;
SSAIfConv IfConv;
public:
diff --git a/llvm/lib/CodeGen/ExpandMemCmp.cpp b/llvm/lib/CodeGen/ExpandMemCmp.cpp
index 6b721a160970e..6ebcc4ff33b95 100644
--- a/llvm/lib/CodeGen/ExpandMemCmp.cpp
+++ b/llvm/lib/CodeGen/ExpandMemCmp.cpp
@@ -71,7 +71,7 @@ class MemCmpExpansion {
ResultBlock() = default;
};
- CallInst *const CI;
+ CallInst *const CI = nullptr;
ResultBlock ResBlock;
const uint64_t Size;
unsigned MaxLoadSize = 0;
@@ -82,7 +82,7 @@ class MemCmpExpansion {
PHINode *PhiRes = nullptr;
const bool IsUsedForZeroCmp;
const DataLayout &DL;
- DomTreeUpdater *DTU;
+ DomTreeUpdater *DTU = nullptr;
IRBuilder<> Builder;
// Represents the decomposition in blocks of the expansion. For example,
// comparing 33 bytes on X86+sse can be done with 2x16-byte loads and
diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
index cc63984158c8a..68a11b4742395 100644
--- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
+++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
@@ -28,8 +28,8 @@ using namespace llvm;
namespace {
struct ExpandPostRA : public MachineFunctionPass {
private:
- const TargetRegisterInfo *TRI;
- const TargetInstrInfo *TII;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
public:
static char ID; // Pass identification, replacement for typeid
diff --git a/llvm/lib/CodeGen/GCRootLowering.cpp b/llvm/lib/CodeGen/GCRootLowering.cpp
index 80feb00454067..c0ce37091933a 100644
--- a/llvm/lib/CodeGen/GCRootLowering.cpp
+++ b/llvm/lib/CodeGen/GCRootLowering.cpp
@@ -52,8 +52,8 @@ class LowerIntrinsics : public FunctionPass {
/// in the machine code. It inserts labels at safe points and populates a
/// GCMetadata record for each function.
class GCMachineCodeAnalysis : public MachineFunctionPass {
- GCFunctionInfo *FI;
- const TargetInstrInfo *TII;
+ GCFunctionInfo *FI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
void FindSafePoints(MachineFunction &MF);
void VisitCallPoint(MachineBasicBlock::iterator CI);
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index 936de316e5754..3016a91f49568 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -189,11 +189,11 @@ namespace {
std::vector<BBInfo> BBAnalysis;
TargetSchedModel SchedModel;
- const TargetLoweringBase *TLI;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const MachineBranchProbabilityInfo *MBPI;
- MachineRegisterInfo *MRI;
+ const TargetLoweringBase *TLI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const MachineBranchProbabilityInfo *MBPI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
LivePhysRegs Redefs;
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
index 53117d63a39b3..1c0926a05958e 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -165,8 +165,8 @@ class InlineSpiller : public Spiller {
const MachineBlockFrequencyInfo &MBFI;
// Variables that are valid during spill(), but used by multiple methods.
- LiveRangeEdit *Edit;
- LiveInterval *StackInt;
+ LiveRangeEdit *Edit = nullptr;
+ LiveInterval *StackInt = nullptr;
int StackSlot;
Register Original;
diff --git a/llvm/lib/CodeGen/InterferenceCache.h b/llvm/lib/CodeGen/InterferenceCache.h
index 97464da9f17b7..c69822d815781 100644
--- a/llvm/lib/CodeGen/InterferenceCache.h
+++ b/llvm/lib/CodeGen/InterferenceCache.h
@@ -54,7 +54,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
unsigned RefCount = 0;
/// MF - The current function.
- MachineFunction *MF;
+ MachineFunction *MF = nullptr;
/// Indexes - Mapping block numbers to SlotIndex ranges.
SlotIndexes *Indexes = nullptr;
diff --git a/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
index d1a53b8c55947..0c0a4e13c7c9e 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/LiveDebugValues.cpp
@@ -81,7 +81,7 @@ class LiveDebugValues : public MachineFunctionPass {
private:
std::unique_ptr<LDVImpl> InstrRefImpl;
std::unique_ptr<LDVImpl> VarLocImpl;
- TargetPassConfig *TPC;
+ TargetPassConfig *TPC = nullptr;
MachineDominatorTree MDT;
};
} // namespace
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index 4f9f5ded367c2..e652105af54ac 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -353,15 +353,15 @@ class MachineBlockPlacement : public MachineFunctionPass {
/// Pair struct containing basic block and taildup profitability
struct BlockAndTailDupResult {
- MachineBasicBlock *BB;
+ MachineBasicBlock *BB = nullptr;
bool ShouldTailDup;
};
/// Triple struct containing edge weight and the edge.
struct WeightedEdge {
BlockFrequency Weight;
- MachineBasicBlock *Src;
- MachineBasicBlock *Dest;
+ MachineBasicBlock *Src = nullptr;
+ MachineBasicBlock *Dest = nullptr;
};
/// work lists of blocks that are ready to be laid out
@@ -372,32 +372,32 @@ class MachineBlockPlacement : public MachineFunctionPass {
DenseMap<const MachineBasicBlock *, BlockAndTailDupResult> ComputedEdges;
/// Machine Function
- MachineFunction *F;
+ MachineFunction *F = nullptr;
/// A handle to the branch probability pass.
- const MachineBranchProbabilityInfo *MBPI;
+ const MachineBranchProbabilityInfo *MBPI = nullptr;
/// A handle to the function-wide block frequency pass.
std::unique_ptr<MBFIWrapper> MBFI;
/// A handle to the loop info.
- MachineLoopInfo *MLI;
+ MachineLoopInfo *MLI = nullptr;
/// Preferred loop exit.
/// Member variable for convenience. It may be removed by duplication deep
/// in the call stack.
- MachineBasicBlock *PreferredLoopExit;
+ MachineBasicBlock *PreferredLoopExit = nullptr;
/// A handle to the target's instruction info.
- const TargetInstrInfo *TII;
+ const TargetInstrInfo *TII = nullptr;
/// A handle to the target's lowering info.
- const TargetLoweringBase *TLI;
+ const TargetLoweringBase *TLI = nullptr;
/// A handle to the post dominator tree.
- MachinePostDominatorTree *MPDT;
+ MachinePostDominatorTree *MPDT = nullptr;
- ProfileSummaryInfo *PSI;
+ ProfileSummaryInfo *PSI = nullptr;
/// Duplicator used to duplicate tails during placement.
///
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index cd86440295307..03e69f83d5e7e 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -68,12 +68,12 @@ static cl::opt<int>
namespace {
class MachineCSE : public MachineFunctionPass {
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- AliasAnalysis *AA;
- MachineDominatorTree *DT;
- MachineRegisterInfo *MRI;
- MachineBlockFrequencyInfo *MBFI;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ AliasAnalysis *AA = nullptr;
+ MachineDominatorTree *DT = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
public:
static char ID; // Pass identification
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index fd02d1b37a358..eb98ccda24875 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -63,16 +63,16 @@ static cl::opt<bool> VerifyPatternOrder(
namespace {
class MachineCombiner : public MachineFunctionPass {
- const TargetSubtargetInfo *STI;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
+ const TargetSubtargetInfo *STI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
MCSchedModel SchedModel;
- MachineRegisterInfo *MRI;
- MachineLoopInfo *MLI; // Current MachineLoopInfo
- MachineTraceMetrics *Traces;
- MachineTraceMetrics::Ensemble *TraceEnsemble;
- MachineBlockFrequencyInfo *MBFI;
- ProfileSummaryInfo *PSI;
+ MachineRegisterInfo *MRI = nullptr;
+ MachineLoopInfo *MLI = nullptr; // Current MachineLoopInfo
+ MachineTraceMetrics *Traces = nullptr;
+ MachineTraceMetrics::Ensemble *TraceEnsemble = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
+ ProfileSummaryInfo *PSI = nullptr;
RegisterClassInfo RegClassInfo;
TargetSchedModel TSchedModel;
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 855c7444b4b7f..5fb52e0366cbd 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -339,9 +339,9 @@ class CopyTracker {
};
class MachineCopyPropagation : public MachineFunctionPass {
- const TargetRegisterInfo *TRI;
- const TargetInstrInfo *TII;
- const MachineRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const MachineRegisterInfo *MRI = nullptr;
// Return true if this is a copy instruction and false otherwise.
bool UseCopyInstr;
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index f730dbd58dc60..56d27b88678ac 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -115,15 +115,15 @@ STATISTIC(NumPostRACopySink, "Number of copies sunk after RA");
namespace {
class MachineSinking : public MachineFunctionPass {
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- MachineRegisterInfo *MRI; // Machine register information
- MachineDominatorTree *DT; // Machine dominator tree
- MachinePostDominatorTree *PDT; // Machine post dominator tree
- MachineCycleInfo *CI;
- MachineBlockFrequencyInfo *MBFI;
- const MachineBranchProbabilityInfo *MBPI;
- AliasAnalysis *AA;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineRegisterInfo *MRI = nullptr; // Machine register information
+ MachineDominatorTree *DT = nullptr; // Machine dominator tree
+ MachinePostDominatorTree *PDT = nullptr; // Machine post dominator tree
+ MachineCycleInfo *CI = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
+ const MachineBranchProbabilityInfo *MBPI = nullptr;
+ AliasAnalysis *AA = nullptr;
RegisterClassInfo RegClassInfo;
// Remember which edges have been considered for breaking.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 84ebcd1be72f9..8eee6b8f6a47e 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -95,12 +95,12 @@ namespace {
Pass *const PASS;
const char *Banner;
- const MachineFunction *MF;
- const TargetMachine *TM;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const MachineRegisterInfo *MRI;
- const RegisterBankInfo *RBI;
+ const MachineFunction *MF = nullptr;
+ const TargetMachine *TM = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const MachineRegisterInfo *MRI = nullptr;
+ const RegisterBankInfo *RBI = nullptr;
unsigned foundErrors;
@@ -115,8 +115,8 @@ namespace {
using RegMap = DenseMap<Register, const MachineInstr *>;
using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
- const MachineInstr *FirstNonPHI;
- const MachineInstr *FirstTerminator;
+ const MachineInstr *FirstNonPHI = nullptr;
+ const MachineInstr *FirstTerminator = nullptr;
BlockSet FunctionBlocks;
BitVector regsReserved;
@@ -208,10 +208,10 @@ namespace {
}
// Analysis information if available
- LiveVariables *LiveVars;
- LiveIntervals *LiveInts;
- LiveStacks *LiveStks;
- SlotIndexes *Indexes;
+ LiveVariables *LiveVars = nullptr;
+ LiveIntervals *LiveInts = nullptr;
+ LiveStacks *LiveStks = nullptr;
+ SlotIndexes *Indexes = nullptr;
void visitMachineFunctionBefore();
void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
diff --git a/llvm/lib/CodeGen/OptimizePHIs.cpp b/llvm/lib/CodeGen/OptimizePHIs.cpp
index e68a6398cf51c..d997fbbed5a68 100644
--- a/llvm/lib/CodeGen/OptimizePHIs.cpp
+++ b/llvm/lib/CodeGen/OptimizePHIs.cpp
@@ -34,8 +34,8 @@ STATISTIC(NumDeadPHICycles, "Number of dead PHI cycles");
namespace {
class OptimizePHIs : public MachineFunctionPass {
- MachineRegisterInfo *MRI;
- const TargetInstrInfo *TII;
+ MachineRegisterInfo *MRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
public:
static char ID; // Pass identification
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index 51035d2e442fb..dbb9a9ffdf60b 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -63,9 +63,9 @@ static cl::opt<bool> NoPhiElimLiveOutEarlyExit(
namespace {
class PHIElimination : public MachineFunctionPass {
- MachineRegisterInfo *MRI; // Machine register information
- LiveVariables *LV;
- LiveIntervals *LIS;
+ MachineRegisterInfo *MRI = nullptr; // Machine register information
+ LiveVariables *LV = nullptr;
+ LiveIntervals *LIS = nullptr;
public:
static char ID; // Pass identification, replacement for typeid
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index c3458be0f8838..a08cc78f11b1b 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -150,11 +150,11 @@ namespace {
class RecurrenceInstr;
class PeepholeOptimizer : public MachineFunctionPass {
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- MachineRegisterInfo *MRI;
- MachineDominatorTree *DT; // Machine dominator tree
- MachineLoopInfo *MLI;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ MachineDominatorTree *DT = nullptr; // Machine dominator tree
+ MachineLoopInfo *MLI = nullptr;
public:
static char ID; // Pass identification
diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
index 7e46dd35ce470..73ad11f1c2f8b 100644
--- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
+++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp
@@ -27,9 +27,9 @@ namespace {
/// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
/// for each use. Add isUndef marker to implicit_def defs and their uses.
class ProcessImplicitDefs : public MachineFunctionPass {
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- MachineRegisterInfo *MRI;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
SmallSetVector<MachineInstr*, 16> WorkList;
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 752cff1665271..98d839b7ad5e3 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -96,7 +96,7 @@ class PEI : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
private:
- RegScavenger *RS;
+ RegScavenger *RS = nullptr;
// MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
// stack frame indexes.
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index dd6f31579f88b..f60e17679f653 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -75,15 +75,15 @@ namespace {
}
private:
- MachineFrameInfo *MFI;
- MachineRegisterInfo *MRI;
- const TargetRegisterInfo *TRI;
- const TargetInstrInfo *TII;
+ MachineFrameInfo *MFI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
RegisterClassInfo RegClassInfo;
const RegClassFilterFunc ShouldAllocateClass;
/// Basic block currently being allocated.
- MachineBasicBlock *MBB;
+ MachineBasicBlock *MBB = nullptr;
/// Maps virtual regs to the frame index where these values are spilled.
IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h
index e0ac88c0aeb92..e54e02f5a8904 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -166,20 +166,20 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
SmallVector<std::pair<const LiveInterval *, MCRegister>, 8>;
// context
- MachineFunction *MF;
+ MachineFunction *MF = nullptr;
// Shortcuts to some useful interface.
- const TargetInstrInfo *TII;
+ const TargetInstrInfo *TII = nullptr;
// analyses
- SlotIndexes *Indexes;
- MachineBlockFrequencyInfo *MBFI;
- MachineDominatorTree *DomTree;
- MachineLoopInfo *Loops;
- MachineOptimizationRemarkEmitter *ORE;
- EdgeBundles *Bundles;
- SpillPlacement *SpillPlacer;
- LiveDebugVariables *DebugVars;
+ SlotIndexes *Indexes = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
+ MachineDominatorTree *DomTree = nullptr;
+ MachineLoopInfo *Loops = nullptr;
+ MachineOptimizationRemarkEmitter *ORE = nullptr;
+ EdgeBundles *Bundles = nullptr;
+ SpillPlacement *SpillPlacer = nullptr;
+ LiveDebugVariables *DebugVars = nullptr;
// state
std::unique_ptr<Spiller> SpillerInstance;
diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp
index 5fd78eccf7323..7394a01e802b3 100644
--- a/llvm/lib/CodeGen/SelectOptimize.cpp
+++ b/llvm/lib/CodeGen/SelectOptimize.cpp
@@ -98,15 +98,15 @@ namespace {
class SelectOptimize : public FunctionPass {
const TargetMachine *TM = nullptr;
- const TargetSubtargetInfo *TSI;
+ const TargetSubtargetInfo *TSI = nullptr;
const TargetLowering *TLI = nullptr;
const TargetTransformInfo *TTI = nullptr;
- const LoopInfo *LI;
- DominatorTree *DT;
+ const LoopInfo *LI = nullptr;
+ DominatorTree *DT = nullptr;
std::unique_ptr<BlockFrequencyInfo> BFI;
std::unique_ptr<BranchProbabilityInfo> BPI;
- ProfileSummaryInfo *PSI;
- OptimizationRemarkEmitter *ORE;
+ ProfileSummaryInfo *PSI = nullptr;
+ OptimizationRemarkEmitter *ORE = nullptr;
TargetSchedModel TSchedModel;
public:
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index c252046ef10bd..31b2f3f5de601 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1744,12 +1744,12 @@ class RegReductionPQBase : public SchedulingPriorityQueue {
bool SrcOrder;
// SUnits - The SUnits for the current graph.
- std::vector<SUnit> *SUnits;
+ std::vector<SUnit> *SUnits = nullptr;
MachineFunction &MF;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const TargetLowering *TLI;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetLowering *TLI = nullptr;
ScheduleDAGRRList *scheduleDAG = nullptr;
// SethiUllmanNumbers - The SethiUllman number for each node.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 5166448974144..20ce2decaad06 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -247,7 +247,7 @@ class SelectionDAGBuilder {
SelectionDAG &DAG;
AAResults *AA = nullptr;
AssumptionCache *AC = nullptr;
- const TargetLibraryInfo *LibInfo;
+ const TargetLibraryInfo *LibInfo = nullptr;
class SDAGSwitchLowering : public SwitchCG::SwitchLowering {
public:
@@ -261,7 +261,7 @@ class SelectionDAGBuilder {
}
private:
- SelectionDAGBuilder *SDB;
+ SelectionDAGBuilder *SDB = nullptr;
};
// Data related to deferred switch lowerings. Used to construct additional
@@ -283,7 +283,7 @@ class SelectionDAGBuilder {
SwiftErrorValueTracking &SwiftError;
/// Garbage collection metadata for the function.
- GCFunctionInfo *GFI;
+ GCFunctionInfo *GFI = nullptr;
/// Map a landing pad to the call site indexes.
DenseMap<MachineBasicBlock *, SmallVector<unsigned, 4>> LPadToCallSiteMap;
@@ -292,7 +292,7 @@ class SelectionDAGBuilder {
/// a tail call. In this case, no subsequent DAG nodes should be created.
bool HasTailCall = false;
- LLVMContext *Context;
+ LLVMContext *Context = nullptr;
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
SwiftErrorValueTracking &swifterror, CodeGenOpt::Level ol)
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index 2411b1ad52031..ffdea3f79aea3 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -110,26 +110,26 @@ namespace {
class ShrinkWrap : public MachineFunctionPass {
/// Hold callee-saved information.
RegisterClassInfo RCI;
- MachineDominatorTree *MDT;
- MachinePostDominatorTree *MPDT;
+ MachineDominatorTree *MDT = nullptr;
+ MachinePostDominatorTree *MPDT = nullptr;
/// Current safe point found for the prologue.
/// The prologue will be inserted before the first instruction
/// in this basic block.
- MachineBasicBlock *Save;
+ MachineBasicBlock *Save = nullptr;
/// Current safe point found for the epilogue.
/// The epilogue will be inserted before the first terminator instruction
/// in this basic block.
- MachineBasicBlock *Restore;
+ MachineBasicBlock *Restore = nullptr;
/// Hold the information of the basic block frequency.
/// Use to check the profitability of the new points.
- MachineBlockFrequencyInfo *MBFI;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
/// Hold the loop information. Used to determine if Save and Restore
/// are in the same loop.
- MachineLoopInfo *MLI;
+ MachineLoopInfo *MLI = nullptr;
// Emit remarks.
MachineOptimizationRemarkEmitter *ORE = nullptr;
@@ -147,7 +147,7 @@ class ShrinkWrap : public MachineFunctionPass {
Register SP;
/// Entry block.
- const MachineBasicBlock *Entry;
+ const MachineBasicBlock *Entry = nullptr;
using SetOfRegs = SmallSetVector<unsigned, 16>;
@@ -155,7 +155,7 @@ class ShrinkWrap : public MachineFunctionPass {
mutable SetOfRegs CurrentCSRs;
/// Current MachineFunction.
- MachineFunction *MachineFunc;
+ MachineFunction *MachineFunc = nullptr;
/// Check if \p MI uses or defines a callee-saved register or
/// a frame index. If this is the case, this means \p MI must happen
diff --git a/llvm/lib/CodeGen/SjLjEHPrepare.cpp b/llvm/lib/CodeGen/SjLjEHPrepare.cpp
index 3fed707a9eb15..d09953e76a808 100644
--- a/llvm/lib/CodeGen/SjLjEHPrepare.cpp
+++ b/llvm/lib/CodeGen/SjLjEHPrepare.cpp
@@ -38,21 +38,21 @@ STATISTIC(NumSpilled, "Number of registers live across unwind edges");
namespace {
class SjLjEHPrepare : public FunctionPass {
- IntegerType *DataTy;
- Type *doubleUnderDataTy;
- Type *doubleUnderJBufTy;
- Type *FunctionContextTy;
+ IntegerType *DataTy = nullptr;
+ Type *doubleUnderDataTy = nullptr;
+ Type *doubleUnderJBufTy = nullptr;
+ Type *FunctionContextTy = nullptr;
FunctionCallee RegisterFn;
FunctionCallee UnregisterFn;
- Function *BuiltinSetupDispatchFn;
- Function *FrameAddrFn;
- Function *StackAddrFn;
- Function *StackRestoreFn;
- Function *LSDAAddrFn;
- Function *CallSiteFn;
- Function *FuncCtxFn;
- AllocaInst *FuncCtx;
- const TargetMachine *TM;
+ Function *BuiltinSetupDispatchFn = nullptr;
+ Function *FrameAddrFn = nullptr;
+ Function *StackAddrFn = nullptr;
+ Function *StackRestoreFn = nullptr;
+ Function *LSDAAddrFn = nullptr;
+ Function *CallSiteFn = nullptr;
+ Function *FuncCtxFn = nullptr;
+ AllocaInst *FuncCtx = nullptr;
+ const TargetMachine *TM = nullptr;
public:
static char ID; // Pass identification, replacement for typeid
diff --git a/llvm/lib/CodeGen/SpillPlacement.h b/llvm/lib/CodeGen/SpillPlacement.h
index d2273a1630256..bd37d85c6c0d6 100644
--- a/llvm/lib/CodeGen/SpillPlacement.h
+++ b/llvm/lib/CodeGen/SpillPlacement.h
@@ -42,15 +42,15 @@ class MachineLoopInfo;
class SpillPlacement : public MachineFunctionPass {
struct Node;
- const MachineFunction *MF;
- const EdgeBundles *bundles;
- const MachineLoopInfo *loops;
- const MachineBlockFrequencyInfo *MBFI;
+ const MachineFunction *MF = nullptr;
+ const EdgeBundles *bundles = nullptr;
+ const MachineLoopInfo *loops = nullptr;
+ const MachineBlockFrequencyInfo *MBFI = nullptr;
Node *nodes = nullptr;
// Nodes that are active in the current computation. Owned by the prepare()
// caller.
- BitVector *ActiveNodes;
+ BitVector *ActiveNodes = nullptr;
// Nodes with active links. Populated by scanActiveBundles.
SmallVector<unsigned, 8> Linked;
diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp
index 11c6bdc699568..3b708a319abf5 100644
--- a/llvm/lib/CodeGen/StackColoring.cpp
+++ b/llvm/lib/CodeGen/StackColoring.cpp
@@ -407,8 +407,8 @@ namespace {
/// StackColoring - A machine pass for merging disjoint stack allocations,
/// marked by the LIFETIME_START and LIFETIME_END pseudo instructions.
class StackColoring : public MachineFunctionPass {
- MachineFrameInfo *MFI;
- MachineFunction *MF;
+ MachineFrameInfo *MFI = nullptr;
+ MachineFunction *MF = nullptr;
/// A class representing liveness information for a single basic block.
/// Each bit in the BitVector represents the liveness property
@@ -448,7 +448,7 @@ class StackColoring : public MachineFunctionPass {
VNInfo::Allocator VNInfoAllocator;
/// SlotIndex analysis object.
- SlotIndexes *Indexes;
+ SlotIndexes *Indexes = nullptr;
/// The list of lifetime markers found. These markers are to be removed
/// once the coloring is done.
diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
index b83c569031338..778ac1f5701ca 100644
--- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
+++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
@@ -48,7 +48,7 @@ namespace {
/// information provided by this pass is optional and not required by the
/// aformentioned intrinsic to function.
class StackMapLiveness : public MachineFunctionPass {
- const TargetRegisterInfo *TRI;
+ const TargetRegisterInfo *TRI = nullptr;
LivePhysRegs LiveRegs;
public:
diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp
index d6c401c3ce33f..6d933ab12041d 100644
--- a/llvm/lib/CodeGen/StackSlotColoring.cpp
+++ b/llvm/lib/CodeGen/StackSlotColoring.cpp
@@ -59,10 +59,10 @@ STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
namespace {
class StackSlotColoring : public MachineFunctionPass {
- LiveStacks* LS;
- MachineFrameInfo *MFI;
- const TargetInstrInfo *TII;
- const MachineBlockFrequencyInfo *MBFI;
+ LiveStacks *LS = nullptr;
+ MachineFrameInfo *MFI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const MachineBlockFrequencyInfo *MBFI = nullptr;
// SSIntervals - Spill slot intervals.
std::vector<LiveInterval*> SSIntervals;
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 256c12176b7f2..92f9505408900 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -87,18 +87,18 @@ static cl::opt<unsigned> MaxDataFlowEdge(
namespace {
class TwoAddressInstructionPass : public MachineFunctionPass {
- MachineFunction *MF;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const InstrItineraryData *InstrItins;
- MachineRegisterInfo *MRI;
- LiveVariables *LV;
- LiveIntervals *LIS;
- AliasAnalysis *AA;
+ MachineFunction *MF = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const InstrItineraryData *InstrItins = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ LiveVariables *LV = nullptr;
+ LiveIntervals *LIS = nullptr;
+ AliasAnalysis *AA = nullptr;
CodeGenOpt::Level OptLevel;
// The current basic block being processed.
- MachineBasicBlock *MBB;
+ MachineBasicBlock *MBB = nullptr;
// Keep track the distance of a MI from the start of the current basic block.
DenseMap<MachineInstr*, unsigned> DistanceMap;
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 8e00712d2308e..8021ca1eb2f13 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -181,14 +181,14 @@ LLVM_DUMP_METHOD void VirtRegMap::dump() const {
namespace {
class VirtRegRewriter : public MachineFunctionPass {
- MachineFunction *MF;
- const TargetRegisterInfo *TRI;
- const TargetInstrInfo *TII;
- MachineRegisterInfo *MRI;
- SlotIndexes *Indexes;
- LiveIntervals *LIS;
- VirtRegMap *VRM;
- LiveDebugVariables *DebugVars;
+ MachineFunction *MF = nullptr;
+ const TargetRegisterInfo *TRI = nullptr;
+ const TargetInstrInfo *TII = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ SlotIndexes *Indexes = nullptr;
+ LiveIntervals *LIS = nullptr;
+ VirtRegMap *VRM = nullptr;
+ LiveDebugVariables *DebugVars = nullptr;
DenseSet<Register> RewriteRegs;
bool ClearVirtRegs;
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