[llvm] 4241d89 - [Target] Use range-based for loops (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 15 14:15:07 PDT 2023
Author: Kazu Hirata
Date: 2023-04-15T14:14:56-07:00
New Revision: 4241d890aec5aba989ef78853bbb0c88c41e2fad
URL: https://github.com/llvm/llvm-project/commit/4241d890aec5aba989ef78853bbb0c88c41e2fad
DIFF: https://github.com/llvm/llvm-project/commit/4241d890aec5aba989ef78853bbb0c88c41e2fad.diff
LOG: [Target] Use range-based for loops (NFC)
Added:
Modified:
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/Sparc/DelaySlotFiller.cpp
llvm/lib/Target/X86/X86FixupLEAs.cpp
llvm/lib/Target/X86/X86RegisterInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index 6c740543f7589..53196c39f296a 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -1033,11 +1033,11 @@ int GCNHazardRecognizer::checkInlineAsmHazards(MachineInstr *IA) {
const MachineRegisterInfo &MRI = MF.getRegInfo();
int WaitStatesNeeded = 0;
- for (unsigned I = InlineAsm::MIOp_FirstOperand, E = IA->getNumOperands();
- I != E; ++I) {
- const MachineOperand &Op = IA->getOperand(I);
+ for (const MachineOperand &Op :
+ llvm::drop_begin(IA->operands(), InlineAsm::MIOp_FirstOperand)) {
if (Op.isReg() && Op.isDef()) {
- WaitStatesNeeded = std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
+ WaitStatesNeeded =
+ std::max(WaitStatesNeeded, checkVALUHazardsHelper(Op, MRI));
}
}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 4a158b31aae23..2ffa540a7e2f8 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1666,8 +1666,8 @@ void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
// Sort the scratch registers into ascending order.
const TargetRegisterInfo &TRI = getRegisterInfo();
SmallVector<unsigned, 6> ScratchRegs;
- for(unsigned I = 5; I < MI->getNumOperands(); ++I)
- ScratchRegs.push_back(MI->getOperand(I).getReg());
+ for (MachineOperand &MO : llvm::drop_begin(MI->operands(), 5))
+ ScratchRegs.push_back(MO.getReg());
llvm::sort(ScratchRegs,
[&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool {
return TRI.getEncodingValue(Reg1) <
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index b4bb7fb295ed7..590612e95f515 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -2119,8 +2119,7 @@ bool ARMConstantIslands::preserveBaseRegister(MachineInstr *JumpMI,
break;
}
- for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
- const MachineOperand &MO = I->getOperand(K);
+ for (const MachineOperand &MO : I->operands()) {
if (!MO.isReg() || !MO.getReg())
continue;
if (MO.isDef() && MO.getReg() == BaseReg)
@@ -2138,8 +2137,7 @@ bool ARMConstantIslands::preserveBaseRegister(MachineInstr *JumpMI,
// Check the add really is removable, and that nothing else in the block
// clobbers BaseReg.
for (++I; &*I != JumpMI; ++I) {
- for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
- const MachineOperand &MO = I->getOperand(K);
+ for (const MachineOperand &MO : I->operands()) {
if (!MO.isReg() || !MO.getReg())
continue;
if (MO.isDef() && MO.getReg() == BaseReg)
@@ -2198,8 +2196,7 @@ static void RemoveDeadAddBetweenLEAAndJT(MachineInstr *LEAMI,
// Ensure EntryReg is not clobbered or used.
MachineBasicBlock::iterator J(RemovableAdd);
for (++J; &*J != JumpMI; ++J) {
- for (unsigned K = 0, E = J->getNumOperands(); K != E; ++K) {
- const MachineOperand &MO = J->getOperand(K);
+ for (const MachineOperand &MO : J->operands()) {
if (!MO.isReg() || !MO.getReg())
continue;
if (MO.isDef() && MO.getReg() == EntryReg)
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 724705c25e3a6..643313daf9288 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -324,8 +324,8 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags());
NewInstr.add(MBBI->getOperand(0));
NewInstr.add(t1CondCodeOp(/*isDead=*/true));
- for (unsigned i = 1, NumOps = MBBI->getNumOperands(); i != NumOps; ++i)
- NewInstr.add(MBBI->getOperand(i));
+ for (MachineOperand &MO : llvm::drop_begin(MBBI->operands()))
+ NewInstr.add(MO);
MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);
MBB->erase(MBBI);
MBBI = NewMBBI;
@@ -437,8 +437,7 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI,
case ARM::VSTMDDB_UPD:
case ARM::VLDMDIA_UPD: {
int First = -1, Last = 0;
- for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
- const MachineOperand &MO = MBBI->getOperand(i);
+ for (const MachineOperand &MO : llvm::drop_begin(MBBI->operands(), 4)) {
unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());
if (First == -1)
First = Reg;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 5b12fff8e9a0a..6024d9f7b1547 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -3119,8 +3119,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
DebugLoc DL = SI->getDebugLoc();
auto MIB = BuildMI(LB, At, DL, HII->get(SI->getOpcode()), NewDR);
- for (unsigned j = 0, m = SI->getNumOperands(); j < m; ++j) {
- const MachineOperand &Op = SI->getOperand(j);
+ for (const MachineOperand &Op : SI->operands()) {
if (!Op.isReg()) {
MIB.add(Op);
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index becc66a4ee90f..6b0315bc1befa 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1059,8 +1059,7 @@ bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
return false;
MachineInstr *OnePhi = I->getParent();
- for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
- const MachineOperand &OPO = OnePhi->getOperand(j);
+ for (const MachineOperand &OPO : OnePhi->operands()) {
if (!OPO.isReg() || !OPO.isDef())
continue;
@@ -1702,8 +1701,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
// operands. Assume that if the compare has a single register use and a
// single immediate operand, then the register is being compared with the
// immediate value.
- for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
- MachineOperand &MO = PredDef->getOperand(i);
+ for (MachineOperand &MO : PredDef->operands()) {
if (MO.isReg()) {
// Skip all implicit references. In one case there was:
// %140 = FCMPUGT32_rr %138, %139, implicit %usr
@@ -1818,8 +1816,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
// Finally, fix the compare instruction.
setImmediate(*CmpImmOp, CmpImm);
- for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
- MachineOperand &MO = PredDef->getOperand(i);
+ for (MachineOperand &MO : PredDef->operands()) {
if (MO.isReg() && MO.getReg() == RB.first) {
MO.setReg(I->first);
return true;
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 2e1a8c39887e2..58d4880642125 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -253,8 +253,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
MachineInstr *UseI = Op.getParent();
if (isFixedInstr(UseI))
continue;
- for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) {
- MachineOperand &MO = UseI->getOperand(i);
+ for (MachineOperand &MO : UseI->operands()) {
// Skip non-registers or registers with subregisters.
if (&MO == &Op || !MO.isReg() || MO.getSubReg())
continue;
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index bb527dca6b6d9..47bab9fd7f5ae 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -351,8 +351,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
RI.getAllocatableSet
(*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
// Exclude all the registers being used by the instruction.
- for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = II->getOperand(i);
+ for (MachineOperand &MO : II->operands()) {
if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
!MO.getReg().isVirtual())
Candidates.reset(MO.getReg());
@@ -367,8 +366,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
// whether the register is live before the instruction. if it's not
// then we don't need to save it in case there are no free registers.
int DefReg = 0;
- for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = II->getOperand(i);
+ for (MachineOperand &MO : II->operands()) {
if (MO.isReg() && MO.isDef()) {
DefReg = MO.getReg();
break;
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 94053fa2eb7a8..8aa5f769c903d 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -321,8 +321,7 @@ static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
/// This function adds registers Filler defines to MBB's live-in register list.
static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
- for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
- const MachineOperand &MO = Filler->getOperand(I);
+ for (const MachineOperand &MO : Filler->operands()) {
unsigned R;
if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 3c0aa23906664..71a3590a50940 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -395,8 +395,7 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
for (MachineBasicBlock &MBB : MF)
for (MachineBasicBlock::iterator MBBI = MBB.end(); MBBI != MBB.begin();) {
--MBBI;
- for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
- MachineOperand &MO = MBBI->getOperand(I);
+ for (MachineOperand &MO : MBBI->operands()) {
if (!MO.isReg())
continue;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 0dd1a8db4cfca..0f96d3c19da4e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1118,8 +1118,7 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg,
if (getPredicatedOpcode(MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
return nullptr;
// Check if MI has any other defs or physreg uses.
- for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (const MachineOperand &MO : llvm::drop_begin(MI->operands())) {
// Reject frame index operands, PEI can't handle the predicated pseudos.
if (MO.isFI() || MO.isCPI() || MO.isJTI())
return nullptr;
diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
index cc132d46de856..7e129101fefc7 100644
--- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -250,8 +250,7 @@ bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
return true;
}
- for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
- const MachineOperand &MO = candidate->getOperand(i);
+ for (const MachineOperand &MO : candidate->operands()) {
if (!MO.isReg())
continue; // skip
diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp
index 5c1ac8dd96715..9137c15316df2 100644
--- a/llvm/lib/Target/X86/X86FixupLEAs.cpp
+++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp
@@ -463,10 +463,8 @@ void FixupLEAPass::checkRegUsage(MachineBasicBlock::iterator &LeaI,
Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg();
Register AluDestReg = AluI->getOperand(0).getReg();
- MachineBasicBlock::iterator CurInst = std::next(LeaI);
- while (CurInst != AluI) {
- for (unsigned I = 0, E = CurInst->getNumOperands(); I != E; ++I) {
- MachineOperand &Opnd = CurInst->getOperand(I);
+ for (MachineInstr &CurInst : llvm::make_range(std::next(LeaI), AluI)) {
+ for (MachineOperand &Opnd : CurInst.operands()) {
if (!Opnd.isReg())
continue;
Register Reg = Opnd.getReg();
@@ -485,7 +483,6 @@ void FixupLEAPass::checkRegUsage(MachineBasicBlock::iterator &LeaI,
*KilledIndex = &Opnd;
}
}
- ++CurInst;
}
}
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 9898ce20e5ac3..2677e5f9446e9 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -932,8 +932,7 @@ unsigned X86RegisterInfo::findDeadCallerSavedReg(
case X86::EH_RETURN:
case X86::EH_RETURN64: {
SmallSet<uint16_t, 8> Uses;
- for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
- MachineOperand &MO = MBBI->getOperand(I);
+ for (MachineOperand &MO : MBBI->operands()) {
if (!MO.isReg() || MO.isDef())
continue;
Register Reg = MO.getReg();
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