[PATCH] D147451: [CodeGen] Enable AArch64 SVE FCMLA/FCADD instruction generation in ComplexDeinterleaving

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 14 09:10:49 PDT 2023

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. I have some minor suggestions but otherwise LGTM.

Comment at: llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp:262
+  /// operation:
+  /// * Using two shufflevectors with even indices for /pReal instruciton and
+  /// odd indices for /pImag instructions (only for fixed-width vectors)
instruciton -> instruction

Comment at: llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp:340
-  if (!TL->isComplexDeinterleavingSupported()) {
+  if (!TL->isComplexDeinterleavingSupported(true) &&
+      !TL->isComplexDeinterleavingSupported(false)) {
I don't think this needs to call with a Scalable flag. The AArch64TargetLowering::isComplexDeinterleavingSupported routine can just return true if it has sve or complexnums.

Comment at: llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp:924
+  auto *ImagShuffle = dyn_cast<ShuffleVectorInst>(Imag);
+  if (RealShuffle && ImagShuffle) {
+    Value *RealOp1 = RealShuffle->getOperand(1);
This could be turned into 
if (!RealShuffle || !ImagShuffle)
  return nullptr;
LLVM often likes returning early to reduce indentation.

  rG LLVM Github Monorepo



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