[llvm] 4fae304 - [X86] Add TESTPS/TESTPD test coverage showing failure to simplify demanded sign bit when the operands has multiple uses

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-04-14T11:29:24+01:00
New Revision: 4fae304d457a2a3c079afa510f83dd87eaa11f9a

URL: https://github.com/llvm/llvm-project/commit/4fae304d457a2a3c079afa510f83dd87eaa11f9a
DIFF: https://github.com/llvm/llvm-project/commit/4fae304d457a2a3c079afa510f83dd87eaa11f9a.diff

LOG: [X86] Add TESTPS/TESTPD test coverage showing failure to simplify demanded sign bit when the operands has multiple uses

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-testpd.ll
    llvm/test/CodeGen/X86/combine-testps.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/combine-testpd.ll b/llvm/test/CodeGen/X86/combine-testpd.ll
index 3a7fbd5f368b1..53e8193d1b3d5 100644
--- a/llvm/test/CodeGen/X86/combine-testpd.ll
+++ b/llvm/test/CodeGen/X86/combine-testpd.ll
@@ -187,6 +187,29 @@ define i32 @testpdz_256_signbit(<4 x double> %c, <4 x double> %d, i32 %a, i32 %b
   ret i32 %t6
 }
 
+define i32 @testpdnzc_256_signbit_multiuse(<4 x double> %c, i32 %a, i32 %b) {
+; CHECK-LABEL: testpdnzc_256_signbit_multiuse:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpcmpgtq %xmm1, %xmm2, %xmm1
+; CHECK-NEXT:    vpcmpgtq %xmm0, %xmm2, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vtestpd %ymm0, %ymm0
+; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %t0 = bitcast <4 x double> %c to <4 x i64>
+  %t1 = icmp sgt <4 x i64> zeroinitializer, %t0
+  %t2 = sext <4 x i1> %t1 to <4 x i64>
+  %t3 = bitcast <4 x i64> %t2 to <4 x double>
+  %t4 = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %t3, <4 x double> %t3)
+  %t5 = icmp ne i32 %t4, 0
+  %t6 = select i1 %t5, i32 %a, i32 %b
+  ret i32 %t6
+}
+
 declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readnone

diff  --git a/llvm/test/CodeGen/X86/combine-testps.ll b/llvm/test/CodeGen/X86/combine-testps.ll
index 6f508f05ac144..6158fc5217969 100644
--- a/llvm/test/CodeGen/X86/combine-testps.ll
+++ b/llvm/test/CodeGen/X86/combine-testps.ll
@@ -187,6 +187,27 @@ define i32 @testpsnzc_256_signbit(<8 x float> %c, <8 x float> %d, i32 %a, i32 %b
   ret i32 %t6
 }
 
+define i32 @testpsc_256_signbit_multiuse(<8 x float> %c, i32 %a, i32 %b) {
+; CHECK-LABEL: testpsc_256_signbit_multiuse:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    vpsrad $31, %xmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpsrad $31, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT:    vtestps %ymm0, %ymm0
+; CHECK-NEXT:    cmovnel %esi, %eax
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %t0 = bitcast <8 x float> %c to <8 x i32>
+  %t1 = ashr <8 x i32> %t0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+  %t2 = bitcast <8 x i32> %t1 to <8 x float>
+  %t3 = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %t2, <8 x float> %t2)
+  %t4 = icmp ne i32 %t3, 0
+  %t5 = select i1 %t4, i32 %a, i32 %b
+  ret i32 %t5
+}
+
 declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone
 declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnone