[PATCH] D148249: [AArch64] Peep SELECT_CC patterns that match smin(a,0) and smax(a,0).

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8952
+    if ((CC == ISD::SETGT || CC == ISD::SETLT) && LHS == TVal &&
+        RHSC && RHSC->isZero() && CFVal && CFVal->isZero() &&
+        LHS.getValueType() == RHS.getValueType()) {
----------------
Is this checking both operands for zero because they might still be different zeroes?


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Comment at: llvm/test/CodeGen/AArch64/min-max-peep.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-ISEL
+; RUN: llc -mtriple=aarch64-eabi %s -o - -mattr=cssc | FileCheck %s --check-prefixes=CHECK,CHECK-ISEL-CSSC
----------------
CHECK would never match both +cssc base cases, but the CSSC cases should all be the same between global and sdag, from the look of it. Can they share the same prefix and remove CHECK?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D148249/new/

https://reviews.llvm.org/D148249