[PATCH] D148234: [AArch64] Remove AND and FMOV between uaddlv an urshl

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

This feels a bit too specific to the exact instructions here, as opposed to the general case. We could change how i64 shifts are represented in the DAG, using v1i64 instead to show that they operate on neon registers. The `and 0xffff` could be removed by teaching it that the uaddlv node only produces zeros in the upper bits (in AArch64TargetLowering::computeKnownBitsForTargetNode). That doesn't solve everything. The representation of aarch64.neon.uaddlv might need to change too, perhaps to produce a v8i16, and something might need to recognize that the upper lanes are zero. That is the part that I'm less sure how it would work.


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  https://reviews.llvm.org/D148234/new/

https://reviews.llvm.org/D148234