[PATCH] D148185: Add more efficient bitwise vector reductions on AArch64

[Markus Everling via Phabricator via llvm-commits]

Sp00ph created this revision.
Sp00ph added reviewers: t.p.northover, nikic, dmgreen.
Herald added subscribers: StephenFan, hiraditya, kristof.beyls.
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Sp00ph requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Improves the codegen for `VECREDUCE_{AND,OR,XOR}` operations on AArch64. Currently, these are fully scalarized, except if the vector is a `<N x i1>`. This patch improves the codegen down to O(log(N)) where N is the length of the vector for vectors whose elements are not `i1`, by repeatedly applying the bitwise operations to the two halves of the vector until only one element is left, which contains the final result. `<N x i1>` bitwise reductions are handled using `VECREDUCE_{UMAX,UMIN,ADD}` instead.

I had to update quite a few codegen tests with these changes, with a general downward trend in instruction count. Since the vector reductions already have tests, I haven't added any new tests myself.

This is my first patch submitted to LLVM, so please tell me if I did anything wrong or if I should change anything.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148185

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
  llvm/test/CodeGen/AArch64/double_reduct.ll
  llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-bool.ll
  llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

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