[PATCH] D147451: [CodeGen] Enable AArch64 SVE FCMLA/FCADD instruction generation in ComplexDeinterleaving

Wed Apr 12 09:59:08 PDT 2023

dmgreen added inline comments.

================
Comment at: llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp:346
+  for (auto &B : F) {
+    if (HasScalableComplexSupport)
+      Changed |= evaluateBasicBlock(&B, true);
----------------
igor.kirillov wrote:
> dmgreen wrote:
> > Does this need to run twice with and without IsScalable? It doubles the scanning of instructions, and seems unnecessary if it only modifies the shuffles/intrinsic matches, which are either both valid or mutually exclusive.
> I thought about it, but theoretically target could have only one (scalable or fixed vector) support.
> Alternatively I can pass both flags `ComplexDeinterleavingGraph` and check them each time root node is found, but I am not sure if it is a better approach.
I'm not sure why that matters. Can you explain more? I would expect that we just match starting from whatever we find (shuffle or intrinsic) and isComplexDeinterleavingOperationSupported handles whether the actual type is supported (be it scalable or fixed length). The shuffle won't ever match a scalable vector, but that shouldn't be a problem as far as I understand.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147451/new/

https://reviews.llvm.org/D147451