[PATCH] D147518: [DAGCombiner] Fix (shl (ctlz x) n) for non-power-of-two Data
Sam Elliott via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 12 09:39:44 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG17cd511007fd: [DAGCombiner] Fix (shl (ctlz x) n) for non-power-of-two Data (authored by lenary).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147518/new/
https://reviews.llvm.org/D147518
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AArch64/pr61549.ll
Index: llvm/test/CodeGen/AArch64/pr61549.ll
===================================================================
--- llvm/test/CodeGen/AArch64/pr61549.ll
+++ llvm/test/CodeGen/AArch64/pr61549.ll
@@ -9,7 +9,9 @@
; CHECK-NEXT: sbfx x9, x0, #0, #35
; CHECK-NEXT: sdiv x10, x8, x9
; CHECK-NEXT: msub x8, x10, x9, x8
-; CHECK-NEXT: eor x0, x8, #0x1
+; CHECK-NEXT: clz x8, x8
+; CHECK-NEXT: sub x8, x8, #29
+; CHECK-NEXT: ubfx x0, x8, #5, #30
; CHECK-NEXT: ret
;
; GISEL-LABEL: f:
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10323,8 +10323,10 @@
return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
}
- // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
+ // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit), and x has a power
+ // of two bitwidth. The "5" represents (log2 (bitwidth x)).
if (N1C && N0.getOpcode() == ISD::CTLZ &&
+ isPowerOf2_32(OpSizeInBits) &&
N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
KnownBits Known = DAG.computeKnownBits(N0.getOperand(0));
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