[llvm] 17cd511 - [DAGCombiner] Fix (shl (ctlz x) n) for non-power-of-two Data

[Archibald Elliott via llvm-commits]

Author: Archibald Elliott
Date: 2023-04-12T17:38:39+01:00
New Revision: 17cd511007fd86cf2a4c5a6e20e1845eb5af3eb8

URL: https://github.com/llvm/llvm-project/commit/17cd511007fd86cf2a4c5a6e20e1845eb5af3eb8
DIFF: https://github.com/llvm/llvm-project/commit/17cd511007fd86cf2a4c5a6e20e1845eb5af3eb8.diff

LOG: [DAGCombiner] Fix (shl (ctlz x) n) for non-power-of-two Data

This DAGCombine is not valid for some combinations of the known bits
of x and non-power-of-two widths of x. As shown in the bug:
- The bitwidth of x is 35 (n=5)
- The unknown bits of x is only the least significant bit
- This gives the result of the ctlz two possible values: 34 or 35, both
  of which will give 1 when left-shifted 5 bits.
- So the `eor x, 1` that this optimisation would give is not correct.

A similar instcombine optimisation is only applied when the width of x is
a power-of-two. GlobalISel does not have this bug, as shown by the testcase.

Fixes #61549

Differential Revision: https://reviews.llvm.org/D147518

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/AArch64/pr61549.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5f3c652750cd..3d11a74627c0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10323,8 +10323,10 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
       return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
   }
 
-  // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit).
+  // fold (srl (ctlz x), "5") -> x  iff x has one bit set (the low bit), and x has a power
+  // of two bitwidth. The "5" represents (log2 (bitwidth x)).
   if (N1C && N0.getOpcode() == ISD::CTLZ &&
+      isPowerOf2_32(OpSizeInBits) &&
       N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
     KnownBits Known = DAG.computeKnownBits(N0.getOperand(0));
 

diff  --git a/llvm/test/CodeGen/AArch64/pr61549.ll b/llvm/test/CodeGen/AArch64/pr61549.ll
index d600e3e742e3..c947706827f8 100644
--- a/llvm/test/CodeGen/AArch64/pr61549.ll
+++ b/llvm/test/CodeGen/AArch64/pr61549.ll
@@ -9,7 +9,9 @@ define i35 @f(i35 %0) {
 ; CHECK-NEXT:    sbfx x9, x0, #0, #35
 ; CHECK-NEXT:    sdiv x10, x8, x9
 ; CHECK-NEXT:    msub x8, x10, x9, x8
-; CHECK-NEXT:    eor x0, x8, #0x1
+; CHECK-NEXT:    clz x8, x8
+; CHECK-NEXT:    sub x8, x8, #29
+; CHECK-NEXT:    ubfx x0, x8, #5, #30
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: f: