[PATCH] D127115: [RFC][DAGCombine] Make sure combined nodes are added back to the worklist in topological order.

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47324
       EVT BCVT = BC.getValueType();
-      assert(BCVT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(BCVT) &&
-             "Unexpected vector type");
+      assert(BCVT.isVector() && "Unexpected vector type");
 
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RKSimon wrote:
> I've removed this assertion in rGb20c1ffe8f3e as part of PR60007
Will rebase.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D127115/new/

https://reviews.llvm.org/D127115