[llvm] dc98330 - [Test] Regenerate checks in some tests using auto-update script

Max Kazantsev via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 11 23:42:39 PDT 2023


Author: Max Kazantsev
Date: 2023-04-12T13:42:31+07:00
New Revision: dc9833067d548f4cd785fe136745cb7aefe0f5b2

URL: https://github.com/llvm/llvm-project/commit/dc9833067d548f4cd785fe136745cb7aefe0f5b2
DIFF: https://github.com/llvm/llvm-project/commit/dc9833067d548f4cd785fe136745cb7aefe0f5b2.diff

LOG: [Test] Regenerate checks in some tests using auto-update script

Added: 
    

Modified: 
    llvm/test/Analysis/ScalarEvolution/guards.ll
    llvm/test/Transforms/IndVarSimplify/iv-sext.ll
    llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Analysis/ScalarEvolution/guards.ll b/llvm/test/Analysis/ScalarEvolution/guards.ll
index 3922775f3c830..ea17c5840067a 100644
--- a/llvm/test/Analysis/ScalarEvolution/guards.ll
+++ b/llvm/test/Analysis/ScalarEvolution/guards.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
 ; RUN: opt -S -passes=indvars < %s | FileCheck %s
 
 ; Check that SCEV is able to recognize and use guards to prove
@@ -13,17 +14,27 @@ declare void @llvm.experimental.guard(i1, ...)
 declare void @use(i64 %x)
 
 define void @test_1(ptr %cond_buf, ptr %len_buf) {
-; CHECK-LABEL: @test_1(
+; CHECK-LABEL: define void @test_1
+; CHECK-SAME: (ptr [[COND_BUF:%.*]], ptr [[LEN_BUF:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[LEN_BUF]], align 4, !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[IV_INC]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 true) [ "deopt"() ]
+; CHECK-NEXT:    [[IV_INC_CMP:%.*]] = icmp ult i32 [[IV_INC]], [[LEN]]
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[IV_INC_CMP]]) [ "deopt"() ]
+; CHECK-NEXT:    [[BECOND:%.*]] = load volatile i1, ptr [[COND_BUF]], align 1
+; CHECK-NEXT:    br i1 [[BECOND]], label [[LOOP]], label [[LEAVE:%.*]]
+; CHECK:       leave:
+; CHECK-NEXT:    ret void
+;
 entry:
   %len = load i32, ptr %len_buf, !range !{i32 1, i32 2147483648}
   br label %loop
 
 loop:
-; CHECK: loop:
-; CHECK:  call void (i1, ...) @llvm.experimental.guard(i1 true) [ "deopt"() ]
-; CHECK:  %iv.inc.cmp = icmp ult i32 %iv.inc, %len
-; CHECK:  call void (i1, ...) @llvm.experimental.guard(i1 %iv.inc.cmp) [ "deopt"() ]
-; CHECK: leave:
 
   %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
   %iv.inc = add i32 %iv, 1
@@ -42,21 +53,30 @@ leave:
 }
 
 define void @test_2(i32 %n, ptr %len_buf) {
-; CHECK-LABEL: @test_2(
-; CHECK:  [[LEN_ZEXT:%[^ ]+]] = zext i32 %len to i64
-; CHECK:  br label %loop
+; CHECK-LABEL: define void @test_2
+; CHECK-SAME: (i32 [[N:%.*]], ptr [[LEN_BUF:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[LEN_BUF]], align 4, !range [[RNG1:![0-9]+]]
+; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[LEN]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[N]] to i64
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT:    call void @use(i64 [[INDVARS_IV]])
+; CHECK-NEXT:    [[IV_INC_CMP:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT]], [[TMP0]]
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[IV_INC_CMP]]) [ "deopt"() ]
+; CHECK-NEXT:    [[BECOND:%.*]] = icmp ne i64 [[INDVARS_IV]], [[TMP1]]
+; CHECK-NEXT:    br i1 [[BECOND]], label [[LOOP]], label [[LEAVE:%.*]]
+; CHECK:       leave:
+; CHECK-NEXT:    ret void
+;
 
 entry:
   %len = load i32, ptr %len_buf, !range !{i32 0, i32 2147483648}
   br label %loop
 
 loop:
-; CHECK: loop:
-; CHECK:  %indvars.iv = phi i64 [ %indvars.iv.next, %loop ], [ 0, %entry ]
-; CHECK:  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
-; CHECK:  %iv.inc.cmp = icmp ult i64 %indvars.iv.next, [[LEN_ZEXT]]
-; CHECK:  call void (i1, ...) @llvm.experimental.guard(i1 %iv.inc.cmp) [ "deopt"() ]
-; CHECK: leave:
 
   %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
   %iv.inc = add i32 %iv, 1
@@ -75,7 +95,24 @@ leave:
 }
 
 define void @test_3(ptr %cond_buf, ptr %len_buf) {
-; CHECK-LABEL: @test_3(
+; CHECK-LABEL: define void @test_3
+; CHECK-SAME: (ptr [[COND_BUF:%.*]], ptr [[LEN_BUF:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[LEN_BUF]], align 4
+; CHECK-NEXT:    [[ENTRY_COND:%.*]] = icmp sgt i32 [[LEN]], 0
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[ENTRY_COND]]) [ "deopt"() ]
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[IV_INC]] = add nsw i32 [[IV]], 1
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 true) [ "deopt"() ]
+; CHECK-NEXT:    [[IV_INC_CMP:%.*]] = icmp slt i32 [[IV_INC]], [[LEN]]
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[IV_INC_CMP]]) [ "deopt"() ]
+; CHECK-NEXT:    [[BECOND:%.*]] = load volatile i1, ptr [[COND_BUF]], align 1
+; CHECK-NEXT:    br i1 [[BECOND]], label [[LOOP]], label [[LEAVE:%.*]]
+; CHECK:       leave:
+; CHECK-NEXT:    ret void
+;
 
 entry:
   %len = load i32, ptr %len_buf
@@ -84,11 +121,6 @@ entry:
   br label %loop
 
 loop:
-; CHECK: loop:
-; CHECK:  call void (i1, ...) @llvm.experimental.guard(i1 true) [ "deopt"() ]
-; CHECK:  %iv.inc.cmp = icmp slt i32 %iv.inc, %len
-; CHECK:  call void (i1, ...) @llvm.experimental.guard(i1 %iv.inc.cmp) [ "deopt"() ]
-; CHECK: leave:
   %iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
   %iv.inc = add i32 %iv, 1
 
@@ -106,7 +138,30 @@ leave:
 }
 
 define void @test_4(ptr %cond_buf, ptr %len_buf) {
-; CHECK-LABEL: @test_4(
+; CHECK-LABEL: define void @test_4
+; CHECK-SAME: (ptr [[COND_BUF:%.*]], ptr [[LEN_BUF:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[LEN_BUF]], align 4
+; CHECK-NEXT:    [[ENTRY_COND:%.*]] = icmp sgt i32 [[LEN]], 0
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[ENTRY_COND]]) [ "deopt"() ]
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[BE:%.*]] ]
+; CHECK-NEXT:    [[IV_INC]] = add i32 [[IV]], 1
+; CHECK-NEXT:    [[COND:%.*]] = load volatile i1, ptr [[COND_BUF]], align 1
+; CHECK-NEXT:    br i1 [[COND]], label [[LEFT:%.*]], label [[BE]]
+; CHECK:       left:
+; CHECK-NEXT:    [[IV_INC_CMP:%.*]] = icmp slt i32 [[IV_INC]], [[LEN]]
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[IV_INC_CMP]]) [ "deopt"() ]
+; CHECK-NEXT:    br label [[BE]]
+; CHECK:       be:
+; CHECK-NEXT:    [[IV_CMP:%.*]] = icmp slt i32 [[IV]], [[LEN]]
+; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 [[IV_CMP]]) [ "deopt"() ]
+; CHECK-NEXT:    [[BECOND:%.*]] = load volatile i1, ptr [[COND_BUF]], align 1
+; CHECK-NEXT:    br i1 [[BECOND]], label [[LOOP]], label [[LEAVE:%.*]]
+; CHECK:       leave:
+; CHECK-NEXT:    ret void
+;
 
 entry:
   %len = load i32, ptr %len_buf
@@ -128,10 +183,6 @@ left:
   br label %be
 
 be:
-; CHECK: be:
-; CHECK-NEXT:  %iv.cmp = icmp slt i32 %iv, %len
-; CHECK-NEXT:  call void (i1, ...) @llvm.experimental.guard(i1 %iv.cmp) [ "deopt"() ]
-; CHECK: leave:
 
   %iv.cmp = icmp slt i32 %iv, %len
   call void(i1, ...) @llvm.experimental.guard(i1 %iv.cmp) [ "deopt"() ]

diff  --git a/llvm/test/Transforms/IndVarSimplify/iv-sext.ll b/llvm/test/Transforms/IndVarSimplify/iv-sext.ll
index 41ca197c25780..450913f16baa2 100644
--- a/llvm/test/Transforms/IndVarSimplify/iv-sext.ll
+++ b/llvm/test/Transforms/IndVarSimplify/iv-sext.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
 ; RUN: opt < %s -passes=indvars -S | FileCheck %s
 
 ; Indvars should be able to promote the hiPart induction variable in the
@@ -6,144 +7,251 @@
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n32:64"
 
-define void @t(ptr %pTmp1, ptr %peakWeight, ptr %nrgReducePeakrate, i32 %bandEdgeIndex, float %tmp1) nounwind {
+define void @t(ptr %pval1, ptr %peakWeight, ptr %nrgReducePeakrate, i32 %bandEdgeIndex, float %val1) nounwind {
+; CHECK-LABEL: define void @t
+; CHECK-SAME: (ptr [[PVAL1:%.*]], ptr [[PEAKWEIGHT:%.*]], ptr [[NRGREDUCEPEAKRATE:%.*]], i32 [[BANDEDGEINDEX:%.*]], float [[VAL1:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[VAL:%.*]] = load float, ptr [[PEAKWEIGHT]], align 4
+; CHECK-NEXT:    [[VAL2:%.*]] = icmp sgt i32 [[BANDEDGEINDEX]], 0
+; CHECK-NEXT:    br i1 [[VAL2]], label [[BB_NPH22:%.*]], label [[RETURN:%.*]]
+; CHECK:       bb.nph22:
+; CHECK-NEXT:    [[VAL3:%.*]] = add i32 [[BANDEDGEINDEX]], -1
+; CHECK-NEXT:    [[TMP0:%.*]] = sext i32 [[VAL3]] to i64
+; CHECK-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[BANDEDGEINDEX]] to i64
+; CHECK-NEXT:    br label [[BB:%.*]]
+; CHECK:       bb:
+; CHECK-NEXT:    [[INDVARS_IV1:%.*]] = phi i64 [ [[INDVARS_IV_NEXT2:%.*]], [[BB8:%.*]] ], [ 0, [[BB_NPH22]] ]
+; CHECK-NEXT:    [[DISTERBHI_121:%.*]] = phi float [ [[DISTERBHI_2_LCSSA:%.*]], [[BB8]] ], [ 0.000000e+00, [[BB_NPH22]] ]
+; CHECK-NEXT:    [[DISTERBLO_120:%.*]] = phi float [ [[DISTERBLO_0_LCSSA:%.*]], [[BB8]] ], [ 0.000000e+00, [[BB_NPH22]] ]
+; CHECK-NEXT:    [[HIPART_119:%.*]] = phi i32 [ [[HIPART_0_LCSSA:%.*]], [[BB8]] ], [ 0, [[BB_NPH22]] ]
+; CHECK-NEXT:    [[LOPART_118:%.*]] = phi i32 [ [[LOPART_0_LCSSA:%.*]], [[BB8]] ], [ 0, [[BB_NPH22]] ]
+; CHECK-NEXT:    [[PEAKCOUNT_117:%.*]] = phi float [ [[PEAKCOUNT_2_LCSSA:%.*]], [[BB8]] ], [ [[VAL]], [[BB_NPH22]] ]
+; CHECK-NEXT:    [[VAL4:%.*]] = icmp ugt i64 [[INDVARS_IV1]], 0
+; CHECK-NEXT:    br i1 [[VAL4]], label [[BB1:%.*]], label [[BB3_PREHEADER:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
+; CHECK-NEXT:    [[VAL7:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[TMP1]]
+; CHECK-NEXT:    [[VAL8:%.*]] = load float, ptr [[VAL7]], align 4
+; CHECK-NEXT:    [[VAL9:%.*]] = fadd float [[VAL8]], [[DISTERBLO_120]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i64 [[INDVARS_IV1]], -1
+; CHECK-NEXT:    [[VAL12:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[TMP2]]
+; CHECK-NEXT:    [[VAL13:%.*]] = load float, ptr [[VAL12]], align 4
+; CHECK-NEXT:    [[VAL14:%.*]] = fsub float [[DISTERBHI_121]], [[VAL13]]
+; CHECK-NEXT:    br label [[BB3_PREHEADER]]
+; CHECK:       bb3.preheader:
+; CHECK-NEXT:    [[DISTERBLO_0_PH:%.*]] = phi float [ [[DISTERBLO_120]], [[BB]] ], [ [[VAL9]], [[BB1]] ]
+; CHECK-NEXT:    [[DISTERBHI_0_PH:%.*]] = phi float [ [[DISTERBHI_121]], [[BB]] ], [ [[VAL14]], [[BB1]] ]
+; CHECK-NEXT:    [[VAL15:%.*]] = fcmp ogt float [[DISTERBLO_0_PH]], 2.500000e+00
+; CHECK-NEXT:    br i1 [[VAL15]], label [[BB_NPH:%.*]], label [[BB5_PREHEADER:%.*]]
+; CHECK:       bb.nph:
+; CHECK-NEXT:    br label [[BB2:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    [[DISTERBLO_03:%.*]] = phi float [ [[VAL19:%.*]], [[BB3:%.*]] ], [ [[DISTERBLO_0_PH]], [[BB_NPH]] ]
+; CHECK-NEXT:    [[LOPART_02:%.*]] = phi i32 [ [[VAL24:%.*]], [[BB3]] ], [ [[LOPART_118]], [[BB_NPH]] ]
+; CHECK-NEXT:    [[PEAKCOUNT_01:%.*]] = phi float [ [[VAL23:%.*]], [[BB3]] ], [ [[PEAKCOUNT_117]], [[BB_NPH]] ]
+; CHECK-NEXT:    [[VAL16:%.*]] = sext i32 [[LOPART_02]] to i64
+; CHECK-NEXT:    [[VAL17:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[VAL16]]
+; CHECK-NEXT:    [[VAL18:%.*]] = load float, ptr [[VAL17]], align 4
+; CHECK-NEXT:    [[VAL19]] = fsub float [[DISTERBLO_03]], [[VAL18]]
+; CHECK-NEXT:    [[VAL20:%.*]] = sext i32 [[LOPART_02]] to i64
+; CHECK-NEXT:    [[VAL21:%.*]] = getelementptr float, ptr [[PEAKWEIGHT]], i64 [[VAL20]]
+; CHECK-NEXT:    [[VAL22:%.*]] = load float, ptr [[VAL21]], align 4
+; CHECK-NEXT:    [[VAL23]] = fsub float [[PEAKCOUNT_01]], [[VAL22]]
+; CHECK-NEXT:    [[VAL24]] = add i32 [[LOPART_02]], 1
+; CHECK-NEXT:    br label [[BB3]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[VAL25:%.*]] = fcmp ogt float [[VAL19]], 2.500000e+00
+; CHECK-NEXT:    br i1 [[VAL25]], label [[BB2]], label [[BB3_BB5_PREHEADER_CRIT_EDGE:%.*]]
+; CHECK:       bb3.bb5.preheader_crit_edge:
+; CHECK-NEXT:    [[VAL24_LCSSA:%.*]] = phi i32 [ [[VAL24]], [[BB3]] ]
+; CHECK-NEXT:    [[VAL23_LCSSA:%.*]] = phi float [ [[VAL23]], [[BB3]] ]
+; CHECK-NEXT:    [[VAL19_LCSSA:%.*]] = phi float [ [[VAL19]], [[BB3]] ]
+; CHECK-NEXT:    br label [[BB5_PREHEADER]]
+; CHECK:       bb5.preheader:
+; CHECK-NEXT:    [[DISTERBLO_0_LCSSA]] = phi float [ [[VAL19_LCSSA]], [[BB3_BB5_PREHEADER_CRIT_EDGE]] ], [ [[DISTERBLO_0_PH]], [[BB3_PREHEADER]] ]
+; CHECK-NEXT:    [[LOPART_0_LCSSA]] = phi i32 [ [[VAL24_LCSSA]], [[BB3_BB5_PREHEADER_CRIT_EDGE]] ], [ [[LOPART_118]], [[BB3_PREHEADER]] ]
+; CHECK-NEXT:    [[PEAKCOUNT_0_LCSSA:%.*]] = phi float [ [[VAL23_LCSSA]], [[BB3_BB5_PREHEADER_CRIT_EDGE]] ], [ [[PEAKCOUNT_117]], [[BB3_PREHEADER]] ]
+; CHECK-NEXT:    [[DOTNOT10:%.*]] = fcmp olt float [[DISTERBHI_0_PH]], 2.500000e+00
+; CHECK-NEXT:    [[VAL26:%.*]] = icmp sgt i32 [[VAL3]], [[HIPART_119]]
+; CHECK-NEXT:    [[OR_COND11:%.*]] = and i1 [[VAL26]], [[DOTNOT10]]
+; CHECK-NEXT:    br i1 [[OR_COND11]], label [[BB_NPH12:%.*]], label [[BB7:%.*]]
+; CHECK:       bb.nph12:
+; CHECK-NEXT:    [[TMP3:%.*]] = sext i32 [[HIPART_119]] to i64
+; CHECK-NEXT:    br label [[BB4:%.*]]
+; CHECK:       bb4:
+; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BB5:%.*]] ], [ [[TMP3]], [[BB_NPH12]] ]
+; CHECK-NEXT:    [[DISTERBHI_29:%.*]] = phi float [ [[VAL30:%.*]], [[BB5]] ], [ [[DISTERBHI_0_PH]], [[BB_NPH12]] ]
+; CHECK-NEXT:    [[PEAKCOUNT_27:%.*]] = phi float [ [[VAL35:%.*]], [[BB5]] ], [ [[PEAKCOUNT_0_LCSSA]], [[BB_NPH12]] ]
+; CHECK-NEXT:    [[VAL28:%.*]] = getelementptr float, ptr [[PVAL1]], i64 [[INDVARS_IV]]
+; CHECK-NEXT:    [[VAL29:%.*]] = load float, ptr [[VAL28]], align 4
+; CHECK-NEXT:    [[VAL30]] = fadd float [[VAL29]], [[DISTERBHI_29]]
+; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT:    [[VAL33:%.*]] = getelementptr float, ptr [[PEAKWEIGHT]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT:    [[VAL34:%.*]] = load float, ptr [[VAL33]], align 4
+; CHECK-NEXT:    [[VAL35]] = fadd float [[VAL34]], [[PEAKCOUNT_27]]
+; CHECK-NEXT:    br label [[BB5]]
+; CHECK:       bb5:
+; CHECK-NEXT:    [[DOTNOT:%.*]] = fcmp olt float [[VAL30]], 2.500000e+00
+; CHECK-NEXT:    [[VAL36:%.*]] = icmp sgt i64 [[TMP0]], [[INDVARS_IV_NEXT]]
+; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[VAL36]], [[DOTNOT]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[BB4]], label [[BB5_BB7_CRIT_EDGE:%.*]]
+; CHECK:       bb5.bb7_crit_edge:
+; CHECK-NEXT:    [[VAL35_LCSSA:%.*]] = phi float [ [[VAL35]], [[BB5]] ]
+; CHECK-NEXT:    [[VAL31_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[BB5]] ]
+; CHECK-NEXT:    [[VAL30_LCSSA:%.*]] = phi float [ [[VAL30]], [[BB5]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = trunc i64 [[VAL31_LCSSA_WIDE]] to i32
+; CHECK-NEXT:    br label [[BB7]]
+; CHECK:       bb7:
+; CHECK-NEXT:    [[DISTERBHI_2_LCSSA]] = phi float [ [[VAL30_LCSSA]], [[BB5_BB7_CRIT_EDGE]] ], [ [[DISTERBHI_0_PH]], [[BB5_PREHEADER]] ]
+; CHECK-NEXT:    [[HIPART_0_LCSSA]] = phi i32 [ [[TMP4]], [[BB5_BB7_CRIT_EDGE]] ], [ [[HIPART_119]], [[BB5_PREHEADER]] ]
+; CHECK-NEXT:    [[PEAKCOUNT_2_LCSSA]] = phi float [ [[VAL35_LCSSA]], [[BB5_BB7_CRIT_EDGE]] ], [ [[PEAKCOUNT_0_LCSSA]], [[BB5_PREHEADER]] ]
+; CHECK-NEXT:    [[VAL37:%.*]] = fadd float [[DISTERBLO_0_LCSSA]], [[DISTERBHI_2_LCSSA]]
+; CHECK-NEXT:    [[VAL38:%.*]] = fdiv float [[PEAKCOUNT_2_LCSSA]], [[VAL37]]
+; CHECK-NEXT:    [[VAL39:%.*]] = fmul float [[VAL38]], [[VAL1]]
+; CHECK-NEXT:    [[VAL40:%.*]] = fmul float [[VAL39]], [[VAL39]]
+; CHECK-NEXT:    [[VAL41:%.*]] = fmul float [[VAL40]], [[VAL40]]
+; CHECK-NEXT:    [[VAL42:%.*]] = fadd float [[VAL41]], 1.000000e+00
+; CHECK-NEXT:    [[VAL43:%.*]] = fdiv float 1.000000e+00, [[VAL42]]
+; CHECK-NEXT:    [[VAL45:%.*]] = getelementptr float, ptr [[NRGREDUCEPEAKRATE]], i64 [[INDVARS_IV1]]
+; CHECK-NEXT:    store float [[VAL43]], ptr [[VAL45]], align 4
+; CHECK-NEXT:    [[INDVARS_IV_NEXT2]] = add nuw nsw i64 [[INDVARS_IV1]], 1
+; CHECK-NEXT:    br label [[BB8]]
+; CHECK:       bb8:
+; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT2]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT:    br i1 [[EXITCOND]], label [[BB]], label [[BB8_RETURN_CRIT_EDGE:%.*]]
+; CHECK:       bb8.return_crit_edge:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    ret void
+;
 entry:
-	%tmp = load float, ptr %peakWeight, align 4		; <float> [#uses=1]
-	%tmp2 = icmp sgt i32 %bandEdgeIndex, 0		; <i1> [#uses=1]
-	br i1 %tmp2, label %bb.nph22, label %return
+  %val = load float, ptr %peakWeight, align 4		; <float> [#uses=1]
+  %val2 = icmp sgt i32 %bandEdgeIndex, 0		; <i1> [#uses=1]
+  br i1 %val2, label %bb.nph22, label %return
 
 bb.nph22:		; preds = %entry
-	%tmp3 = add i32 %bandEdgeIndex, -1		; <i32> [#uses=2]
-	br label %bb
+  %val3 = add i32 %bandEdgeIndex, -1		; <i32> [#uses=2]
+  br label %bb
 
-; CHECK: bb:
-; CHECK: phi i64
-; CHECK-NOT: phi i64
 bb:		; preds = %bb8, %bb.nph22
-	%distERBhi.121 = phi float [ %distERBhi.2.lcssa, %bb8 ], [ 0.000000e+00, %bb.nph22 ]		; <float> [#uses=2]
-	%distERBlo.120 = phi float [ %distERBlo.0.lcssa, %bb8 ], [ 0.000000e+00, %bb.nph22 ]		; <float> [#uses=2]
-	%hiPart.119 = phi i32 [ %hiPart.0.lcssa, %bb8 ], [ 0, %bb.nph22 ]		; <i32> [#uses=3]
-	%loPart.118 = phi i32 [ %loPart.0.lcssa, %bb8 ], [ 0, %bb.nph22 ]		; <i32> [#uses=2]
-	%peakCount.117 = phi float [ %peakCount.2.lcssa, %bb8 ], [ %tmp, %bb.nph22 ]		; <float> [#uses=2]
-	%part.016 = phi i32 [ %tmp46, %bb8 ], [ 0, %bb.nph22 ]		; <i32> [#uses=5]
-	%tmp4 = icmp sgt i32 %part.016, 0		; <i1> [#uses=1]
-	br i1 %tmp4, label %bb1, label %bb3.preheader
-
-; CHECK: bb1:
+  %distERBhi.121 = phi float [ %distERBhi.2.lcssa, %bb8 ], [ 0.000000e+00, %bb.nph22 ]		; <float> [#uses=2]
+  %distERBlo.120 = phi float [ %distERBlo.0.lcssa, %bb8 ], [ 0.000000e+00, %bb.nph22 ]		; <float> [#uses=2]
+  %hiPart.119 = phi i32 [ %hiPart.0.lcssa, %bb8 ], [ 0, %bb.nph22 ]		; <i32> [#uses=3]
+  %loPart.118 = phi i32 [ %loPart.0.lcssa, %bb8 ], [ 0, %bb.nph22 ]		; <i32> [#uses=2]
+  %peakCount.117 = phi float [ %peakCount.2.lcssa, %bb8 ], [ %val, %bb.nph22 ]		; <float> [#uses=2]
+  %part.016 = phi i32 [ %val46, %bb8 ], [ 0, %bb.nph22 ]		; <i32> [#uses=5]
+  %val4 = icmp sgt i32 %part.016, 0		; <i1> [#uses=1]
+  br i1 %val4, label %bb1, label %bb3.preheader
+
 bb1:		; preds = %bb
-	%tmp5 = add i32 %part.016, -1		; <i32> [#uses=1]
-	%tmp6 = sext i32 %tmp5 to i64		; <i64> [#uses=1]
-	%tmp7 = getelementptr float, ptr %pTmp1, i64 %tmp6		; <ptr> [#uses=1]
-	%tmp8 = load float, ptr %tmp7, align 4		; <float> [#uses=1]
-	%tmp9 = fadd float %tmp8, %distERBlo.120		; <float> [#uses=1]
-	%tmp10 = add i32 %part.016, -1		; <i32> [#uses=1]
-	%tmp11 = sext i32 %tmp10 to i64		; <i64> [#uses=1]
-	%tmp12 = getelementptr float, ptr %pTmp1, i64 %tmp11		; <ptr> [#uses=1]
-	%tmp13 = load float, ptr %tmp12, align 4		; <float> [#uses=1]
-	%tmp14 = fsub float %distERBhi.121, %tmp13		; <float> [#uses=1]
-	br label %bb3.preheader
+  %val5 = add i32 %part.016, -1		; <i32> [#uses=1]
+  %val6 = sext i32 %val5 to i64		; <i64> [#uses=1]
+  %val7 = getelementptr float, ptr %pval1, i64 %val6		; <ptr> [#uses=1]
+  %val8 = load float, ptr %val7, align 4		; <float> [#uses=1]
+  %val9 = fadd float %val8, %distERBlo.120		; <float> [#uses=1]
+  %val10 = add i32 %part.016, -1		; <i32> [#uses=1]
+  %val11 = sext i32 %val10 to i64		; <i64> [#uses=1]
+  %val12 = getelementptr float, ptr %pval1, i64 %val11		; <ptr> [#uses=1]
+  %val13 = load float, ptr %val12, align 4		; <float> [#uses=1]
+  %val14 = fsub float %distERBhi.121, %val13		; <float> [#uses=1]
+  br label %bb3.preheader
 
 bb3.preheader:		; preds = %bb1, %bb
-	%distERBlo.0.ph = phi float [ %distERBlo.120, %bb ], [ %tmp9, %bb1 ]		; <float> [#uses=3]
-	%distERBhi.0.ph = phi float [ %distERBhi.121, %bb ], [ %tmp14, %bb1 ]		; <float> [#uses=3]
-	%tmp15 = fcmp ogt float %distERBlo.0.ph, 2.500000e+00		; <i1> [#uses=1]
-	br i1 %tmp15, label %bb.nph, label %bb5.preheader
+  %distERBlo.0.ph = phi float [ %distERBlo.120, %bb ], [ %val9, %bb1 ]		; <float> [#uses=3]
+  %distERBhi.0.ph = phi float [ %distERBhi.121, %bb ], [ %val14, %bb1 ]		; <float> [#uses=3]
+  %val15 = fcmp ogt float %distERBlo.0.ph, 2.500000e+00		; <i1> [#uses=1]
+  br i1 %val15, label %bb.nph, label %bb5.preheader
 
 bb.nph:		; preds = %bb3.preheader
-	br label %bb2
+  br label %bb2
 
 bb2:		; preds = %bb3, %bb.nph
-	%distERBlo.03 = phi float [ %tmp19, %bb3 ], [ %distERBlo.0.ph, %bb.nph ]		; <float> [#uses=1]
-	%loPart.02 = phi i32 [ %tmp24, %bb3 ], [ %loPart.118, %bb.nph ]		; <i32> [#uses=3]
-	%peakCount.01 = phi float [ %tmp23, %bb3 ], [ %peakCount.117, %bb.nph ]		; <float> [#uses=1]
-	%tmp16 = sext i32 %loPart.02 to i64		; <i64> [#uses=1]
-	%tmp17 = getelementptr float, ptr %pTmp1, i64 %tmp16		; <ptr> [#uses=1]
-	%tmp18 = load float, ptr %tmp17, align 4		; <float> [#uses=1]
-	%tmp19 = fsub float %distERBlo.03, %tmp18		; <float> [#uses=3]
-	%tmp20 = sext i32 %loPart.02 to i64		; <i64> [#uses=1]
-	%tmp21 = getelementptr float, ptr %peakWeight, i64 %tmp20		; <ptr> [#uses=1]
-	%tmp22 = load float, ptr %tmp21, align 4		; <float> [#uses=1]
-	%tmp23 = fsub float %peakCount.01, %tmp22		; <float> [#uses=2]
-	%tmp24 = add i32 %loPart.02, 1		; <i32> [#uses=2]
-	br label %bb3
+  %distERBlo.03 = phi float [ %val19, %bb3 ], [ %distERBlo.0.ph, %bb.nph ]		; <float> [#uses=1]
+  %loPart.02 = phi i32 [ %val24, %bb3 ], [ %loPart.118, %bb.nph ]		; <i32> [#uses=3]
+  %peakCount.01 = phi float [ %val23, %bb3 ], [ %peakCount.117, %bb.nph ]		; <float> [#uses=1]
+  %val16 = sext i32 %loPart.02 to i64		; <i64> [#uses=1]
+  %val17 = getelementptr float, ptr %pval1, i64 %val16		; <ptr> [#uses=1]
+  %val18 = load float, ptr %val17, align 4		; <float> [#uses=1]
+  %val19 = fsub float %distERBlo.03, %val18		; <float> [#uses=3]
+  %val20 = sext i32 %loPart.02 to i64		; <i64> [#uses=1]
+  %val21 = getelementptr float, ptr %peakWeight, i64 %val20		; <ptr> [#uses=1]
+  %val22 = load float, ptr %val21, align 4		; <float> [#uses=1]
+  %val23 = fsub float %peakCount.01, %val22		; <float> [#uses=2]
+  %val24 = add i32 %loPart.02, 1		; <i32> [#uses=2]
+  br label %bb3
 
 bb3:		; preds = %bb2
-	%tmp25 = fcmp ogt float %tmp19, 2.500000e+00		; <i1> [#uses=1]
-	br i1 %tmp25, label %bb2, label %bb3.bb5.preheader_crit_edge
+  %val25 = fcmp ogt float %val19, 2.500000e+00		; <i1> [#uses=1]
+  br i1 %val25, label %bb2, label %bb3.bb5.preheader_crit_edge
 
 bb3.bb5.preheader_crit_edge:		; preds = %bb3
-	%tmp24.lcssa = phi i32 [ %tmp24, %bb3 ]		; <i32> [#uses=1]
-	%tmp23.lcssa = phi float [ %tmp23, %bb3 ]		; <float> [#uses=1]
-	%tmp19.lcssa = phi float [ %tmp19, %bb3 ]		; <float> [#uses=1]
-	br label %bb5.preheader
+  %val24.lcssa = phi i32 [ %val24, %bb3 ]		; <i32> [#uses=1]
+  %val23.lcssa = phi float [ %val23, %bb3 ]		; <float> [#uses=1]
+  %val19.lcssa = phi float [ %val19, %bb3 ]		; <float> [#uses=1]
+  br label %bb5.preheader
 
 bb5.preheader:		; preds = %bb3.bb5.preheader_crit_edge, %bb3.preheader
-	%distERBlo.0.lcssa = phi float [ %tmp19.lcssa, %bb3.bb5.preheader_crit_edge ], [ %distERBlo.0.ph, %bb3.preheader ]		; <float> [#uses=2]
-	%loPart.0.lcssa = phi i32 [ %tmp24.lcssa, %bb3.bb5.preheader_crit_edge ], [ %loPart.118, %bb3.preheader ]		; <i32> [#uses=1]
-	%peakCount.0.lcssa = phi float [ %tmp23.lcssa, %bb3.bb5.preheader_crit_edge ], [ %peakCount.117, %bb3.preheader ]		; <float> [#uses=2]
-	%.not10 = fcmp olt float %distERBhi.0.ph, 2.500000e+00		; <i1> [#uses=1]
-	%tmp26 = icmp sgt i32 %tmp3, %hiPart.119		; <i1> [#uses=1]
-	%or.cond11 = and i1 %tmp26, %.not10		; <i1> [#uses=1]
-	br i1 %or.cond11, label %bb.nph12, label %bb7
+  %distERBlo.0.lcssa = phi float [ %val19.lcssa, %bb3.bb5.preheader_crit_edge ], [ %distERBlo.0.ph, %bb3.preheader ]		; <float> [#uses=2]
+  %loPart.0.lcssa = phi i32 [ %val24.lcssa, %bb3.bb5.preheader_crit_edge ], [ %loPart.118, %bb3.preheader ]		; <i32> [#uses=1]
+  %peakCount.0.lcssa = phi float [ %val23.lcssa, %bb3.bb5.preheader_crit_edge ], [ %peakCount.117, %bb3.preheader ]		; <float> [#uses=2]
+  %.not10 = fcmp olt float %distERBhi.0.ph, 2.500000e+00		; <i1> [#uses=1]
+  %val26 = icmp sgt i32 %val3, %hiPart.119		; <i1> [#uses=1]
+  %or.cond11 = and i1 %val26, %.not10		; <i1> [#uses=1]
+  br i1 %or.cond11, label %bb.nph12, label %bb7
 
 bb.nph12:		; preds = %bb5.preheader
-	br label %bb4
-; CHECK: bb4:
-; CHECK: phi i64
-; CHECK-NOT: phi i64
-; CHECK-NOT: sext
+  br label %bb4
 bb4:		; preds = %bb5, %bb.nph12
-	%distERBhi.29 = phi float [ %tmp30, %bb5 ], [ %distERBhi.0.ph, %bb.nph12 ]		; <float> [#uses=1]
-	%hiPart.08 = phi i32 [ %tmp31, %bb5 ], [ %hiPart.119, %bb.nph12 ]		; <i32> [#uses=2]
-	%peakCount.27 = phi float [ %tmp35, %bb5 ], [ %peakCount.0.lcssa, %bb.nph12 ]		; <float> [#uses=1]
-	%tmp27 = sext i32 %hiPart.08 to i64		; <i64> [#uses=1]
-	%tmp28 = getelementptr float, ptr %pTmp1, i64 %tmp27		; <ptr> [#uses=1]
-	%tmp29 = load float, ptr %tmp28, align 4		; <float> [#uses=1]
-	%tmp30 = fadd float %tmp29, %distERBhi.29		; <float> [#uses=3]
-	%tmp31 = add i32 %hiPart.08, 1		; <i32> [#uses=4]
-	%tmp32 = sext i32 %tmp31 to i64		; <i64> [#uses=1]
-	%tmp33 = getelementptr float, ptr %peakWeight, i64 %tmp32		; <ptr> [#uses=1]
-	%tmp34 = load float, ptr %tmp33, align 4		; <float> [#uses=1]
-	%tmp35 = fadd float %tmp34, %peakCount.27		; <float> [#uses=2]
-	br label %bb5
-
-; CHECK: bb5:
+  %distERBhi.29 = phi float [ %val30, %bb5 ], [ %distERBhi.0.ph, %bb.nph12 ]		; <float> [#uses=1]
+  %hiPart.08 = phi i32 [ %val31, %bb5 ], [ %hiPart.119, %bb.nph12 ]		; <i32> [#uses=2]
+  %peakCount.27 = phi float [ %val35, %bb5 ], [ %peakCount.0.lcssa, %bb.nph12 ]		; <float> [#uses=1]
+  %val27 = sext i32 %hiPart.08 to i64		; <i64> [#uses=1]
+  %val28 = getelementptr float, ptr %pval1, i64 %val27		; <ptr> [#uses=1]
+  %val29 = load float, ptr %val28, align 4		; <float> [#uses=1]
+  %val30 = fadd float %val29, %distERBhi.29		; <float> [#uses=3]
+  %val31 = add i32 %hiPart.08, 1		; <i32> [#uses=4]
+  %val32 = sext i32 %val31 to i64		; <i64> [#uses=1]
+  %val33 = getelementptr float, ptr %peakWeight, i64 %val32		; <ptr> [#uses=1]
+  %val34 = load float, ptr %val33, align 4		; <float> [#uses=1]
+  %val35 = fadd float %val34, %peakCount.27		; <float> [#uses=2]
+  br label %bb5
+
 bb5:		; preds = %bb4
-	%.not = fcmp olt float %tmp30, 2.500000e+00		; <i1> [#uses=1]
-	%tmp36 = icmp sgt i32 %tmp3, %tmp31		; <i1> [#uses=1]
-	%or.cond = and i1 %tmp36, %.not		; <i1> [#uses=1]
-	br i1 %or.cond, label %bb4, label %bb5.bb7_crit_edge
+  %.not = fcmp olt float %val30, 2.500000e+00		; <i1> [#uses=1]
+  %val36 = icmp sgt i32 %val3, %val31		; <i1> [#uses=1]
+  %or.cond = and i1 %val36, %.not		; <i1> [#uses=1]
+  br i1 %or.cond, label %bb4, label %bb5.bb7_crit_edge
 
 bb5.bb7_crit_edge:		; preds = %bb5
-	%tmp35.lcssa = phi float [ %tmp35, %bb5 ]		; <float> [#uses=1]
-	%tmp31.lcssa = phi i32 [ %tmp31, %bb5 ]		; <i32> [#uses=1]
-	%tmp30.lcssa = phi float [ %tmp30, %bb5 ]		; <float> [#uses=1]
-	br label %bb7
+  %val35.lcssa = phi float [ %val35, %bb5 ]		; <float> [#uses=1]
+  %val31.lcssa = phi i32 [ %val31, %bb5 ]		; <i32> [#uses=1]
+  %val30.lcssa = phi float [ %val30, %bb5 ]		; <float> [#uses=1]
+  br label %bb7
 
 bb7:		; preds = %bb5.bb7_crit_edge, %bb5.preheader
-	%distERBhi.2.lcssa = phi float [ %tmp30.lcssa, %bb5.bb7_crit_edge ], [ %distERBhi.0.ph, %bb5.preheader ]		; <float> [#uses=2]
-	%hiPart.0.lcssa = phi i32 [ %tmp31.lcssa, %bb5.bb7_crit_edge ], [ %hiPart.119, %bb5.preheader ]		; <i32> [#uses=1]
-	%peakCount.2.lcssa = phi float [ %tmp35.lcssa, %bb5.bb7_crit_edge ], [ %peakCount.0.lcssa, %bb5.preheader ]		; <float> [#uses=2]
-	%tmp37 = fadd float %distERBlo.0.lcssa, %distERBhi.2.lcssa		; <float> [#uses=1]
-	%tmp38 = fdiv float %peakCount.2.lcssa, %tmp37		; <float> [#uses=1]
-	%tmp39 = fmul float %tmp38, %tmp1		; <float> [#uses=2]
-	%tmp40 = fmul float %tmp39, %tmp39		; <float> [#uses=2]
-	%tmp41 = fmul float %tmp40, %tmp40		; <float> [#uses=1]
-	%tmp42 = fadd float %tmp41, 1.000000e+00		; <float> [#uses=1]
-	%tmp43 = fdiv float 1.000000e+00, %tmp42		; <float> [#uses=1]
-	%tmp44 = sext i32 %part.016 to i64		; <i64> [#uses=1]
-	%tmp45 = getelementptr float, ptr %nrgReducePeakrate, i64 %tmp44		; <ptr> [#uses=1]
-	store float %tmp43, ptr %tmp45, align 4
-	%tmp46 = add i32 %part.016, 1		; <i32> [#uses=2]
-	br label %bb8
+  %distERBhi.2.lcssa = phi float [ %val30.lcssa, %bb5.bb7_crit_edge ], [ %distERBhi.0.ph, %bb5.preheader ]		; <float> [#uses=2]
+  %hiPart.0.lcssa = phi i32 [ %val31.lcssa, %bb5.bb7_crit_edge ], [ %hiPart.119, %bb5.preheader ]		; <i32> [#uses=1]
+  %peakCount.2.lcssa = phi float [ %val35.lcssa, %bb5.bb7_crit_edge ], [ %peakCount.0.lcssa, %bb5.preheader ]		; <float> [#uses=2]
+  %val37 = fadd float %distERBlo.0.lcssa, %distERBhi.2.lcssa		; <float> [#uses=1]
+  %val38 = fdiv float %peakCount.2.lcssa, %val37		; <float> [#uses=1]
+  %val39 = fmul float %val38, %val1		; <float> [#uses=2]
+  %val40 = fmul float %val39, %val39		; <float> [#uses=2]
+  %val41 = fmul float %val40, %val40		; <float> [#uses=1]
+  %val42 = fadd float %val41, 1.000000e+00		; <float> [#uses=1]
+  %val43 = fdiv float 1.000000e+00, %val42		; <float> [#uses=1]
+  %val44 = sext i32 %part.016 to i64		; <i64> [#uses=1]
+  %val45 = getelementptr float, ptr %nrgReducePeakrate, i64 %val44		; <ptr> [#uses=1]
+  store float %val43, ptr %val45, align 4
+  %val46 = add i32 %part.016, 1		; <i32> [#uses=2]
+  br label %bb8
 
 bb8:		; preds = %bb7
-	%tmp47 = icmp slt i32 %tmp46, %bandEdgeIndex		; <i1> [#uses=1]
-	br i1 %tmp47, label %bb, label %bb8.return_crit_edge
+  %val47 = icmp slt i32 %val46, %bandEdgeIndex		; <i1> [#uses=1]
+  br i1 %val47, label %bb, label %bb8.return_crit_edge
 
 bb8.return_crit_edge:		; preds = %bb8
-	br label %return
+  br label %return
 
 return:		; preds = %bb8.return_crit_edge, %entry
-	ret void
+  ret void
 }

diff  --git a/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll b/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll
index 5eef9cb00369a..208a587171a96 100644
--- a/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll
+++ b/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll
@@ -12,7 +12,7 @@
 define void @test_predicated_simple_unsigned(ptr %p, ptr %arr) {
 ; CHECK-LABEL: @test_predicated_simple_unsigned(
 ; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4, [[RNG0:!range !.*]]
+; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4, !range [[RNG0:![0-9]+]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[LEN]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -61,7 +61,7 @@ fail:
 define void @test_predicated_simple_signed(ptr %p, ptr %arr) {
 ; CHECK-LABEL: @test_predicated_simple_signed(
 ; CHECK-NEXT:  preheader:
-; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4, [[RNG0]]
+; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4, !range [[RNG0]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[LEN]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -470,7 +470,7 @@ define void @test_can_predicate_simple_unsigned(ptr %p, ptr %arr) {
 ; CHECK-NEXT:  preheader:
 ; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[LEN]], -1
-; CHECK-NEXT:    [[RANGE_CHECK1:%.*]] = icmp ult i32 [[TMP0]], [[LEN]]
+; CHECK-NEXT:    [[RANGE_CHECK_FIRST_ITER:%.*]] = icmp ult i32 [[TMP0]], [[LEN]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[LEN]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -478,7 +478,7 @@ define void @test_can_predicate_simple_unsigned(ptr %p, ptr %arr) {
 ; CHECK-NEXT:    br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]]
 ; CHECK:       range_check_block:
 ; CHECK-NEXT:    [[IV_NEXT]] = sub i32 [[IV]], 1
-; CHECK-NEXT:    br i1 [[RANGE_CHECK1]], label [[BACKEDGE]], label [[FAIL:%.*]]
+; CHECK-NEXT:    br i1 [[RANGE_CHECK_FIRST_ITER]], label [[BACKEDGE]], label [[FAIL:%.*]]
 ; CHECK:       backedge:
 ; CHECK-NEXT:    [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
 ; CHECK-NEXT:    [[EL:%.*]] = load i32, ptr [[EL_PTR]], align 4
@@ -521,7 +521,7 @@ define void @test_can_predicate_simple_unsigned_inverted(ptr %p, ptr %arr) {
 ; CHECK-NEXT:  preheader:
 ; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[LEN]], -1
-; CHECK-NEXT:    [[RANGE_CHECK1:%.*]] = icmp uge i32 [[TMP0]], [[LEN]]
+; CHECK-NEXT:    [[RANGE_CHECK_FIRST_ITER:%.*]] = icmp uge i32 [[TMP0]], [[LEN]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[LEN]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -529,7 +529,7 @@ define void @test_can_predicate_simple_unsigned_inverted(ptr %p, ptr %arr) {
 ; CHECK-NEXT:    br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]]
 ; CHECK:       range_check_block:
 ; CHECK-NEXT:    [[IV_NEXT]] = sub i32 [[IV]], 1
-; CHECK-NEXT:    br i1 [[RANGE_CHECK1]], label [[FAIL:%.*]], label [[BACKEDGE]]
+; CHECK-NEXT:    br i1 [[RANGE_CHECK_FIRST_ITER]], label [[FAIL:%.*]], label [[BACKEDGE]]
 ; CHECK:       backedge:
 ; CHECK-NEXT:    [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
 ; CHECK-NEXT:    [[EL:%.*]] = load i32, ptr [[EL_PTR]], align 4
@@ -624,7 +624,7 @@ define void @test_can_predicate_trunc_unsigned(ptr %p, ptr %arr) {
 ; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    [[START:%.*]] = zext i32 [[LEN]] to i64
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[LEN]], -1
-; CHECK-NEXT:    [[RANGE_CHECK1:%.*]] = icmp ult i32 [[TMP0]], [[LEN]]
+; CHECK-NEXT:    [[RANGE_CHECK_FIRST_ITER:%.*]] = icmp ult i32 [[TMP0]], [[LEN]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[START]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -632,7 +632,7 @@ define void @test_can_predicate_trunc_unsigned(ptr %p, ptr %arr) {
 ; CHECK-NEXT:    br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]]
 ; CHECK:       range_check_block:
 ; CHECK-NEXT:    [[IV_NEXT]] = sub nsw i64 [[IV]], 1
-; CHECK-NEXT:    br i1 [[RANGE_CHECK1]], label [[BACKEDGE]], label [[FAIL:%.*]]
+; CHECK-NEXT:    br i1 [[RANGE_CHECK_FIRST_ITER]], label [[BACKEDGE]], label [[FAIL:%.*]]
 ; CHECK:       backedge:
 ; CHECK-NEXT:    [[EL_PTR:%.*]] = getelementptr i32, ptr [[ARR:%.*]], i64 [[IV]]
 ; CHECK-NEXT:    [[EL:%.*]] = load i32, ptr [[EL_PTR]], align 4
@@ -678,7 +678,7 @@ define void @test_can_predicate_trunc_unsigned_inverted(ptr %p, ptr %arr) {
 ; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    [[START:%.*]] = zext i32 [[LEN]] to i64
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[LEN]], -1
-; CHECK-NEXT:    [[RANGE_CHECK1:%.*]] = icmp uge i32 [[TMP0]], [[LEN]]
+; CHECK-NEXT:    [[RANGE_CHECK_FIRST_ITER:%.*]] = icmp uge i32 [[TMP0]], [[LEN]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[START]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -686,7 +686,7 @@ define void @test_can_predicate_trunc_unsigned_inverted(ptr %p, ptr %arr) {
 ; CHECK-NEXT:    br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]]
 ; CHECK:       range_check_block:
 ; CHECK-NEXT:    [[IV_NEXT]] = sub nsw i64 [[IV]], 1
-; CHECK-NEXT:    br i1 [[RANGE_CHECK1]], label [[FAIL:%.*]], label [[BACKEDGE]]
+; CHECK-NEXT:    br i1 [[RANGE_CHECK_FIRST_ITER]], label [[FAIL:%.*]], label [[BACKEDGE]]
 ; CHECK:       backedge:
 ; CHECK-NEXT:    [[EL_PTR:%.*]] = getelementptr i32, ptr [[ARR:%.*]], i64 [[IV]]
 ; CHECK-NEXT:    [[EL:%.*]] = load i32, ptr [[EL_PTR]], align 4
@@ -835,7 +835,7 @@ define void @test_can_predicate_simple_unsigned_
diff erent_start(i32 %start, ptr
 ; CHECK-NEXT:  preheader:
 ; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[START:%.*]], -1
-; CHECK-NEXT:    [[RANGE_CHECK1:%.*]] = icmp ult i32 [[TMP0]], [[LEN]]
+; CHECK-NEXT:    [[RANGE_CHECK_FIRST_ITER:%.*]] = icmp ult i32 [[TMP0]], [[LEN]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[START]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -843,7 +843,7 @@ define void @test_can_predicate_simple_unsigned_
diff erent_start(i32 %start, ptr
 ; CHECK-NEXT:    br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]]
 ; CHECK:       range_check_block:
 ; CHECK-NEXT:    [[IV_NEXT]] = sub i32 [[IV]], 1
-; CHECK-NEXT:    br i1 [[RANGE_CHECK1]], label [[BACKEDGE]], label [[FAIL:%.*]]
+; CHECK-NEXT:    br i1 [[RANGE_CHECK_FIRST_ITER]], label [[BACKEDGE]], label [[FAIL:%.*]]
 ; CHECK:       backedge:
 ; CHECK-NEXT:    [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
 ; CHECK-NEXT:    [[EL:%.*]] = load i32, ptr [[EL_PTR]], align 4
@@ -886,7 +886,7 @@ define void @test_can_predicate_simple_unsigned_inverted_
diff erent_start(i32 %st
 ; CHECK-NEXT:  preheader:
 ; CHECK-NEXT:    [[LEN:%.*]] = load i32, ptr [[P:%.*]], align 4
 ; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[START:%.*]], -1
-; CHECK-NEXT:    [[RANGE_CHECK1:%.*]] = icmp uge i32 [[TMP0]], [[LEN]]
+; CHECK-NEXT:    [[RANGE_CHECK_FIRST_ITER:%.*]] = icmp uge i32 [[TMP0]], [[LEN]]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
 ; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ [[START]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
@@ -894,7 +894,7 @@ define void @test_can_predicate_simple_unsigned_inverted_
diff erent_start(i32 %st
 ; CHECK-NEXT:    br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]]
 ; CHECK:       range_check_block:
 ; CHECK-NEXT:    [[IV_NEXT]] = sub i32 [[IV]], 1
-; CHECK-NEXT:    br i1 [[RANGE_CHECK1]], label [[FAIL:%.*]], label [[BACKEDGE]]
+; CHECK-NEXT:    br i1 [[RANGE_CHECK_FIRST_ITER]], label [[FAIL:%.*]], label [[BACKEDGE]]
 ; CHECK:       backedge:
 ; CHECK-NEXT:    [[EL_PTR:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
 ; CHECK-NEXT:    [[EL:%.*]] = load i32, ptr [[EL_PTR]], align 4


        


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