[llvm] a38b2d7 - [RISCV][Tablegen] Make VLXSched and VSXSched classes aware of data and index lmul

[Nitin John Raj via llvm-commits]

Author: Nitin John Raj
Date: 2023-04-11T10:53:40-07:00
New Revision: a38b2d77610fe4541892e335230611772399f83e

URL: https://github.com/llvm/llvm-project/commit/a38b2d77610fe4541892e335230611772399f83e
DIFF: https://github.com/llvm/llvm-project/commit/a38b2d77610fe4541892e335230611772399f83e.diff

LOG: [RISCV][Tablegen] Make VLXSched and VSXSched classes aware of data and index lmul

The LMUL for data and index are not guaranteed the same so we need different LMULs appended to the sched classes for them.

Differential Revision: https://reviews.llvm.org/D147814

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 5605d821ee04..29555936e6ff 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -125,16 +125,20 @@ class VSSSched<int n, string suffix = "WorstCase"> : Sched<[
   ReadVSTX, ReadVSTSX, ReadVMask
 ]>;
 
-class VLXSched<int n, string o, string suffix = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVLD" #o #"X" #n #"_" # suffix),
+class VLXSched<int n, string o,
+               string dataSuffix = "WorstCase",
+               string idxSuffix = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVLD" #o #"X" #n #"_" # dataSuffix),
   ReadVLDX,
-  !cast<SchedReadWrite>("ReadVLD" #o #"XV_" # suffix), ReadVMask
+  !cast<SchedReadWrite>("ReadVLD" #o #"XV_" # idxSuffix), ReadVMask
 ]>;
 
-class VSXSched<int n, string o, string suffix = "WorstCase"> : Sched<[
-  !cast<SchedReadWrite>("WriteVST" #o #"X" #n #"_"#suffix),
-  !cast<SchedReadWrite>("ReadVST" #o #"X" #n #"_"#suffix),
-  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV_"#suffix), ReadVMask
+class VSXSched<int n, string o,
+               string dataSuffix = "WorstCase",
+               string idxSuffix = "WorstCase"> : Sched<[
+  !cast<SchedReadWrite>("WriteVST" #o #"X" #n #"_"#dataSuffix),
+  !cast<SchedReadWrite>("ReadVST" #o #"X" #n #"_"#dataSuffix),
+  ReadVSTX, !cast<SchedReadWrite>("ReadVST" #o #"XV_"#idxSuffix), ReadVMask
 ]>;
 
 class VLFSched<string suffix = "WorstCase"> : Sched<[

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 4055404c71a4..758c37d96378 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1735,7 +1735,7 @@ multiclass VPseudoILoad<bit Ordered> {
         // Calculate emul = eew * lmul / sew
         defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-          defvar LInfo = lmul.MX;
+          defvar DataLInfo = lmul.MX;
           defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = lmul.vrclass;
@@ -1743,16 +1743,16 @@ multiclass VPseudoILoad<bit Ordered> {
           defvar HasConstraint = !ne(sew, eew);
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = lmul.value in {
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoILoadNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
-              VLXSched<eew, Order, LInfo>;
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_TU":
+              VLXSched<eew, Order, DataLInfo, IdxLInfo>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_TU":
               VPseudoILoadNoMaskTU<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
-              VLXSched<eew, Order, LInfo>;
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
+              VLXSched<eew, Order, DataLInfo, IdxLInfo>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoILoadMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered, HasConstraint>,
               RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
-              VLXSched<eew, Order, LInfo>;
+              VLXSched<eew, Order, DataLInfo, IdxLInfo>;
           }
         }
       }
@@ -1809,19 +1809,19 @@ multiclass VPseudoIStore<bit Ordered> {
         // Calculate emul = eew * lmul / sew
         defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2<sew>.val);
         if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
-          defvar LInfo = lmul.MX;
+          defvar DataLInfo = lmul.MX;
           defvar IdxLInfo = octuple_to_str<octuple_emul>.ret;
           defvar idx_lmul = !cast<LMULInfo>("V_" # IdxLInfo);
           defvar Vreg = lmul.vrclass;
           defvar IdxVreg = idx_lmul.vrclass;
           defvar Order = !if(Ordered, "O", "U");
           let VLMul = lmul.value in {
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo :
               VPseudoIStoreNoMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>,
-              VSXSched<eew, Order, LInfo>;
-            def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
+              VSXSched<eew, Order, DataLInfo, IdxLInfo>;
+            def "EI" # eew # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
               VPseudoIStoreMask<Vreg, IdxVreg, eew, idx_lmul.value, Ordered>,
-              VSXSched<eew, Order, LInfo>;
+              VSXSched<eew, Order, DataLInfo, IdxLInfo>;
           }
         }
       }