[PATCH] D145301: Add more efficient vector bitcast for AArch64

[Lawrence Benson via Phabricator via llvm-commits]

lawben updated this revision to Diff 512204.
lawben added a comment.

Changed approach as suggested by @dmgreen. We now use an explicit sign-extend and ignore the vector compare. The sign-extend is removed in later steps if there is a vector compare, 
so there is no overhead. This change allows us to determine the original type in more cases, as we can detect both `SETCC` and `TRUNC`.

Added a few more tests, also explicitly checking <64-bit vectors and <8-bit elements.

Just as an FYI for the tests: the sign-extend is implemented as a shift left by size-1 bits and a signed comparison <0, which is true if the MSB is set.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145301/new/

https://reviews.llvm.org/D145301

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll

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