[PATCH] D147887: Summary: Teach the AArch64 backend patterns to generate the RAX1 instruction.

[Shreyansh Chouhan via Phabricator via llvm-commits]

BK1603 updated this revision to Diff 512197.
BK1603 added a comment.

D147887 <https://reviews.llvm.org/D147887>: Summary: Teach the AArch64 backend patterns to generate the RAX1 instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147887/new/

https://reviews.llvm.org/D147887

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/rax1.ll


Index: llvm/test/CodeGen/AArch64/rax1.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/rax1.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+
+define <2 x i64> @rax1(<2 x i64> %x, <2 x i64> %y) {
+; SHA3-LABEL: rax1:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    rax1 v0.2d, v0.2d, v1.2d
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: rax1:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    ushr v2.2d, v1.2d, #63
+; NOSHA3-NEXT:    shl v1.2d, v1.2d, #1
+; NOSHA3-NEXT:    orr v1.16b, v1.16b, v2.16b
+; NOSHA3-NEXT:    eor v0.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    ret
+    %a = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %y, <2 x i64> %y, <2 x i64> <i64 1, i64 1>)
+    %b = xor <2 x i64> %x, %a
+    ret <2 x i64> %b
+}
+
+declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1273,6 +1273,8 @@
 def : Pat<(v2i64 (int_aarch64_crypto_xar (v2i64 V128:$Vn), (v2i64 V128:$Vm), (i64 timm0_63:$imm))),
           (XAR (v2i64 V128:$Vn), (v2i64 V128:$Vm), (timm0_63:$imm))>;
 
+def : Pat<(xor  (v2i64 V128:$Vn), (or (AArch64vlshr (v2i64 V128:$Vm), (i32 63)), (AArch64vshl (v2i64 V128:$Vm), (i32 1)))),
+          (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
 
 } // HasSHA3
 


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