[PATCH] D147877: [AVR] Reject invalid LDD instruction with explicit error
Ben Shi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 9 02:59:21 PDT 2023
benshi001 created this revision.
benshi001 added reviewers: aykevl, Miss_Grape.
Herald added subscribers: Jim, hiraditya, dylanmckay.
Herald added a project: All.
benshi001 requested review of this revision.
Herald added subscribers: llvm-commits, jacquesguan.
Herald added a project: LLVM.
We should reject `ldd Rn, X` with explicit error message
rather than `llvm_unreachable`.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D147877
Files:
llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
Index: llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
===================================================================
--- llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
+++ llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
@@ -1,4 +1,5 @@
-; RUN: not llc < %s -march=avr -no-integrated-as 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=avr -mcpu=avr6 -filetype=obj -no-integrated-as 2>&1 \
+; RUN: | FileCheck %s
define void @foo(i16 %a) {
; CHECK: error: invalid operand in inline asm: 'jl ${0:l}'
@@ -13,3 +14,9 @@
call i16 asm sideeffect ";; ${0:C}", "=d"()
ret void
}
+
+define void @foo2() {
+ ; CHECK: error: expected either Y or Z register
+ call void asm sideeffect "ldd r24, X+2", ""()
+ ret void
+}
Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
+++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp
@@ -146,7 +146,8 @@
switch (RegOp.getReg()) {
default:
- llvm_unreachable("Expected either Y or Z register");
+ Ctx.reportError(MI.getLoc(), "expected either Y or Z register");
+ return 0;
case AVR::R31R30:
RegBit = 0;
break; // Z register
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