[PATCH] D76354: [RISCV][GlobalISel] Legalize types for ALU operations

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

LGTM with some nits. I also still think this isn't the best strategy for handling 32-bit ops for 64 but changing that should also change the DAG path



================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:31
+  bool IsRV64 = ST.is64Bit();
+  const LLT &XLenLLT = IsRV64 ? s64 : s32;
+
----------------
Don't use reference to LLT


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:49
+    // on RV32 we use a libcall.
+    if (IsRV64)
+      getActionDefinitionsBuilder({G_MUL, G_SDIV, G_SREM, G_UDIV, G_UREM})
----------------
Braces 


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:105
+
+  MIRBuilder.setInstr(MI);
+
----------------
I believe this is pre-set for you


================
Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:123
+
+  MIRBuilder.setInstr(MI);
+
----------------
I believe this is pre-set for you


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76354/new/

https://reviews.llvm.org/D76354