[PATCH] D146915: Implement TypeSig generator in `Intrinsics.td`

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/include/llvm/IR/Intrinsics.td:185
 
+// (Idx << 3) | ArgCode
+class EncAnyType<int ArgCode=0> {
----------------
I don't know what Idx means here in relation to the constant 0x100


================
Comment at: llvm/include/llvm/IR/Intrinsics.td:215
+  int ax
+> {
+  int ah = !and(ax, 0xFF00);
----------------
Should be on previous line


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Comment at: llvm/include/llvm/IR/Intrinsics.td:607
+  list<LLVMType> ParamTypes
+> {
+  list<LLVMType> AllTypes = !listconcat(RetTypes, ParamTypes);
----------------
Ditto


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Comment at: llvm/utils/TableGen/CodeGenIntrinsics.cpp:123
 
+#define OLD 1
+
----------------
chapuni wrote:
> arsenm wrote:
> > Leftover dead code?
> Two reason.
> 
> * I would like to notify to downstreams with this change.
> * I would like to leave the history for someone to visit.
> 
> I could squash D145937 into this.
I don't expect the encoding of intrinsics to be a meaningful place for downstream users. Ok as long as the OLD stuff is removed in the next patch 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146915/new/

https://reviews.llvm.org/D146915