[llvm] 985e24c - [AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-04-08T08:39:21+01:00
New Revision: 985e24cc16ecc35540ecff0efd23bf0abc328f66

URL: https://github.com/llvm/llvm-project/commit/985e24cc16ecc35540ecff0efd23bf0abc328f66
DIFF: https://github.com/llvm/llvm-project/commit/985e24cc16ecc35540ecff0efd23bf0abc328f66.diff

LOG: [AMDGPU] Fix a case of updating LiveIntervals in SIOptimizeExecMaskingPreRA

This was causing two test failures when I applied D129208 to enable
extra verification of LiveIntervals:

  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir
  LLVM :: CodeGen/AMDGPU/optimize-negated-cond-exec-masking.mir

Differential Revision: https://reviews.llvm.org/D147721

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index bffbf9d584ea..710e36bbf024 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -294,7 +294,13 @@ bool SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {
 
       LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());
       LIS->RemoveMachineInstrFromMaps(*Sel);
+      bool ShrinkSel = Sel->getOperand(0).readsReg();
       Sel->eraseFromParent();
+      if (ShrinkSel) {
+        // The result of the V_CNDMASK was a subreg def which counted as a read
+        // from the other parts of the reg. Shrink their live ranges.
+        LIS->shrinkToUses(SelLI);
+      }
     }
   }