[PATCH] D147168: [AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALU

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

LGTM with nit



================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:6190-6191
 
-    case AMDGPU::S_BREV_B64:
-      splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_BREV_B32, true);
-      Inst.eraseFromParent();
-      continue;
+  // Deferred list of instructions will be processed once
+  // all the MachineInstr in the worklist are done.
+  for (MachineInstr *Inst : Worklist.getDeferredList()) {
----------------
Doesn't explain why these are deferred 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D147168/new/

https://reviews.llvm.org/D147168