[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 7 08:36:38 PDT 2023
luke added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll:339-341
%a = load <4 x i16>, ptr %x, align 1
%b.gep = getelementptr i8, ptr %x, i64 %s
%b = load <4 x i16>, ptr %b.gep, align 1
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@reames FYI, this mirrors the loads from SLP in x264 SAD which have an alignment of 1
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D147713/new/
https://reviews.llvm.org/D147713
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