[PATCH] D147712: [RISCV] Add tests for concats of vectors that could become strided loads

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 511676.
luke added a comment.

Add some more tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147712/new/

https://reviews.llvm.org/D147712

Files:
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

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