[PATCH] D147713: [RISCV] Combine concat_vectors of loads into strided loads

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll:237
   ret void
 }
----------------
reames wrote:
> Can you add a couple of negative tests?
> 
> 1) A case where the stride is not equal.  (i.e. we recognize stride mismatch.)
> 
> 2) A case where the resulting type is not legal.
> 
> 3) A case with a non-simple load.  
> 
> 4) A case where one of the operands is not a load.
I'm struggling to think of ways to get an illegal result type.
We can produce an illegal type when we concat an irregular number of vectors so we get something like `3 x v4i16 -> v12i16`, which is covered by `widen_3xv4i16`, but in that case we never actually do the combine in the first place since it doesn't have a concat_vector that we can match on.
`strided_constant_v4i32` handles the case where we would have tried to a strided load of `v2i128`.

Did you have a specific example in mind?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147713/new/

https://reviews.llvm.org/D147713